This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it.
Cc: Jason Liu jason.hui.liu@nxp.com Cc: Ye Li ye.li@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mx6/Kconfig | 4 - board/freescale/mx6qarm2/Kconfig | 12 - board/freescale/mx6qarm2/MAINTAINERS | 10 - board/freescale/mx6qarm2/Makefile | 7 - board/freescale/mx6qarm2/imximage.cfg | 337 -------------- board/freescale/mx6qarm2/imximage_mx6dl.cfg | 461 -------------------- board/freescale/mx6qarm2/mx6qarm2.c | 290 ------------ configs/mx6dlarm2_defconfig | 41 -- configs/mx6dlarm2_lpddr2_defconfig | 41 -- configs/mx6qarm2_defconfig | 41 -- configs/mx6qarm2_lpddr2_defconfig | 41 -- include/configs/mx6qarm2.h | 127 ------ 12 files changed, 1412 deletions(-) delete mode 100644 board/freescale/mx6qarm2/Kconfig delete mode 100644 board/freescale/mx6qarm2/MAINTAINERS delete mode 100644 board/freescale/mx6qarm2/Makefile delete mode 100644 board/freescale/mx6qarm2/imximage.cfg delete mode 100644 board/freescale/mx6qarm2/imximage_mx6dl.cfg delete mode 100644 board/freescale/mx6qarm2/mx6qarm2.c delete mode 100644 configs/mx6dlarm2_defconfig delete mode 100644 configs/mx6dlarm2_lpddr2_defconfig delete mode 100644 configs/mx6qarm2_defconfig delete mode 100644 configs/mx6qarm2_lpddr2_defconfig delete mode 100644 include/configs/mx6qarm2.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 594923e804c2..b0923ef76edb 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -287,9 +287,6 @@ config TARGET_MX6MEMCAL and characterize the memory layout of a new design during the initial development and pre-production stages.
-config TARGET_MX6QARM2 - bool "mx6qarm2" - config TARGET_MX6DL_MAMOJ bool "Support BTicino Mamoj" depends on MX6QDL @@ -622,7 +619,6 @@ source "board/compulab/cm_fx6/Kconfig" source "board/dhelectronics/dh_imx6/Kconfig" source "board/engicam/imx6q/Kconfig" source "board/engicam/imx6ul/Kconfig" -source "board/freescale/mx6qarm2/Kconfig" source "board/freescale/mx6memcal/Kconfig" source "board/freescale/mx6sabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" diff --git a/board/freescale/mx6qarm2/Kconfig b/board/freescale/mx6qarm2/Kconfig deleted file mode 100644 index 8ab8b460f92a..000000000000 --- a/board/freescale/mx6qarm2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MX6QARM2 - -config SYS_BOARD - default "mx6qarm2" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx6qarm2" - -endif diff --git a/board/freescale/mx6qarm2/MAINTAINERS b/board/freescale/mx6qarm2/MAINTAINERS deleted file mode 100644 index fdbc7fa7254b..000000000000 --- a/board/freescale/mx6qarm2/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -MX6QARM2 BOARD -M: Jason Liu jason.hui.liu@nxp.com -M: Ye Li ye.li@nxp.com -S: Maintained -F: board/freescale/mx6qarm2/ -F: include/configs/mx6qarm2.h -F: configs/mx6qarm2_defconfig -F: configs/mx6dlarm2_defconfig -F: configs/mx6qarm2_lpddr2_defconfig -F: configs/mx6dlarm2_lpddr2_defconfig diff --git a/board/freescale/mx6qarm2/Makefile b/board/freescale/mx6qarm2/Makefile deleted file mode 100644 index ef80a8967258..000000000000 --- a/board/freescale/mx6qarm2/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -obj-y := mx6qarm2.o diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg deleted file mode 100644 index 74a33c25032a..000000000000 --- a/board/freescale/mx6qarm2/imximage.cfg +++ /dev/null @@ -1,337 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. - * Jason Liu r64343@freescale.com - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -#ifdef CONFIG_MX6DQ_LPDDR2 -/* DCD */ -DATA 4 0x020C4018 0x60324 - -DATA 4 0x020E05a8 0x00003038 -DATA 4 0x020E05b0 0x00003038 -DATA 4 0x020E0524 0x00003038 -DATA 4 0x020E051c 0x00003038 - -DATA 4 0x020E0518 0x00003038 -DATA 4 0x020E050c 0x00003038 -DATA 4 0x020E05b8 0x00003038 -DATA 4 0x020E05c0 0x00003038 - -DATA 4 0x020E05ac 0x00000038 -DATA 4 0x020E05b4 0x00000038 -DATA 4 0x020E0528 0x00000038 -DATA 4 0x020E0520 0x00000038 - -DATA 4 0x020E0514 0x00000038 -DATA 4 0x020E0510 0x00000038 -DATA 4 0x020E05bc 0x00000038 -DATA 4 0x020E05c4 0x00000038 - -DATA 4 0x020E056c 0x00000038 -DATA 4 0x020E0578 0x00000038 -DATA 4 0x020E0588 0x00000038 -DATA 4 0x020E0594 0x00000038 - -DATA 4 0x020E057c 0x00000038 -DATA 4 0x020E0590 0x00000038 -DATA 4 0x020E0598 0x00000038 -DATA 4 0x020E058c 0x00000000 - -DATA 4 0x020E059c 0x00000038 -DATA 4 0x020E05a0 0x00000038 -DATA 4 0x020E0784 0x00000038 -DATA 4 0x020E0788 0x00000038 - -DATA 4 0x020E0794 0x00000038 -DATA 4 0x020E079c 0x00000038 -DATA 4 0x020E07a0 0x00000038 -DATA 4 0x020E07a4 0x00000038 - -DATA 4 0x020E07a8 0x00000038 -DATA 4 0x020E0748 0x00000038 -DATA 4 0x020E074c 0x00000038 -DATA 4 0x020E0750 0x00020000 - -DATA 4 0x020E0758 0x00000000 -DATA 4 0x020E0774 0x00020000 -DATA 4 0x020E078c 0x00000038 -DATA 4 0x020E0798 0x00080000 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b401c 0x00008000 - -DATA 4 0x021b085c 0x1b5f01ff -DATA 4 0x021b485c 0x1b5f01ff - -DATA 4 0x021b0800 0xa1390000 -DATA 4 0x021b4800 0xa1390000 - -DATA 4 0x021b0890 0x00400000 -DATA 4 0x021b4890 0x00400000 - -DATA 4 0x021b48bc 0x00055555 - -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 - -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 - -DATA 4 0x021b082c 0xf3333333 -DATA 4 0x021b0830 0xf3333333 -DATA 4 0x021b0834 0xf3333333 -DATA 4 0x021b0838 0xf3333333 -DATA 4 0x021b482c 0xf3333333 -DATA 4 0x021b4830 0xf3333333 -DATA 4 0x021b4834 0xf3333333 -DATA 4 0x021b4838 0xf3333333 - -DATA 4 0x021b0848 0x49383b39 -DATA 4 0x021b0850 0x30364738 -DATA 4 0x021b4848 0x3e3c3846 -DATA 4 0x021b4850 0x4c294b35 - -DATA 4 0x021b083c 0x20000000 -DATA 4 0x021b0840 0x0 -DATA 4 0x021b483c 0x20000000 -DATA 4 0x021b4840 0x0 - -DATA 4 0x021b0858 0xf00 -DATA 4 0x021b4858 0xf00 - -DATA 4 0x021b08b8 0x800 -DATA 4 0x021b48b8 0x800 - -DATA 4 0x021b000c 0x555a61a5 -DATA 4 0x021b0004 0x20036 -DATA 4 0x021b0010 0x160e83 -DATA 4 0x021b0014 0xdd -DATA 4 0x021b0018 0x8174c -DATA 4 0x021b002c 0xf9f26d2 -DATA 4 0x021b0030 0x20e -DATA 4 0x021b0038 0x200aac -DATA 4 0x021b0008 0x0 - -DATA 4 0x021b0040 0x5f - -DATA 4 0x021b0000 0xc3010000 - -DATA 4 0x021b400c 0x555a61a5 -DATA 4 0x021b4004 0x20036 -DATA 4 0x021b4010 0x160e83 -DATA 4 0x021b4014 0xdd -DATA 4 0x021b4018 0x8174c -DATA 4 0x021b402c 0xf9f26d2 -DATA 4 0x021b4030 0x20e -DATA 4 0x021b4038 0x200aac -DATA 4 0x021b4008 0x0 - -DATA 4 0x021b4040 0x3f -DATA 4 0x021b4000 0xc3010000 - -DATA 4 0x021b001c 0x3f8030 -DATA 4 0x021b001c 0xff0a8030 -DATA 4 0x021b001c 0xc2018030 -DATA 4 0x021b001c 0x6028030 -DATA 4 0x021b001c 0x2038030 - -DATA 4 0x021b401c 0x3f8030 -DATA 4 0x021b401c 0xff0a8030 -DATA 4 0x021b401c 0xc2018030 -DATA 4 0x021b401c 0x6028030 -DATA 4 0x021b401c 0x2038030 - -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b4800 0xa1390003 - -DATA 4 0x021b0020 0x7800 -DATA 4 0x021b4020 0x7800 - -DATA 4 0x021b0818 0x0 -DATA 4 0x021b4818 0x0 - -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b4800 0xa1390003 - -DATA 4 0x021b08b8 0x800 -DATA 4 0x021b48b8 0x800 - -DATA 4 0x021b001c 0x0 -DATA 4 0x021b401c 0x0 - -DATA 4 0x021b0404 0x00011006 - -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F - -#else -DATA 4 0x020e05a8 0x00000030 -DATA 4 0x020e05b0 0x00000030 -DATA 4 0x020e0524 0x00000030 -DATA 4 0x020e051c 0x00000030 - -DATA 4 0x020e0518 0x00000030 -DATA 4 0x020e050c 0x00000030 -DATA 4 0x020e05b8 0x00000030 -DATA 4 0x020e05c0 0x00000030 - -DATA 4 0x020e05ac 0x00020030 -DATA 4 0x020e05b4 0x00020030 -DATA 4 0x020e0528 0x00020030 -DATA 4 0x020e0520 0x00020030 - -DATA 4 0x020e0514 0x00020030 -DATA 4 0x020e0510 0x00020030 -DATA 4 0x020e05bc 0x00020030 -DATA 4 0x020e05c4 0x00020030 - -DATA 4 0x020e056c 0x00020030 -DATA 4 0x020e0578 0x00020030 -DATA 4 0x020e0588 0x00020030 -DATA 4 0x020e0594 0x00020030 - -DATA 4 0x020e057c 0x00020030 -DATA 4 0x020e0590 0x00003000 -DATA 4 0x020e0598 0x00003000 -DATA 4 0x020e058c 0x00000000 - -DATA 4 0x020e059c 0x00003030 -DATA 4 0x020e05a0 0x00003030 -DATA 4 0x020e0784 0x00000030 -DATA 4 0x020e0788 0x00000030 - -DATA 4 0x020e0794 0x00000030 -DATA 4 0x020e079c 0x00000030 -DATA 4 0x020e07a0 0x00000030 -DATA 4 0x020e07a4 0x00000030 - -DATA 4 0x020e07a8 0x00000030 -DATA 4 0x020e0748 0x00000030 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e0750 0x00020000 - -DATA 4 0x020e0758 0x00000000 -DATA 4 0x020e0774 0x00020000 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0798 0x000C0000 - -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 - -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 - -DATA 4 0x021b0018 0x00081740 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538E64 -DATA 4 0x021b0014 0x01FF00DB -DATA 4 0x021b002c 0x000026D2 - -DATA 4 0x021b0030 0x005B0E21 -DATA 4 0x021b0008 0x09444040 -DATA 4 0x021b0004 0x00025576 -DATA 4 0x021b0040 0x00000027 -DATA 4 0x021b0000 0xC31A0000 - -DATA 4 0x021b001c 0x04088032 -DATA 4 0x021b001c 0x0408803A -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x0000803B -DATA 4 0x021b001c 0x00428031 -DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x09408030 -DATA 4 0x021b001c 0x09408038 - -DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b001c 0x04008048 -DATA 4 0x021b0800 0xA1380003 -DATA 4 0x021b4800 0xA1380003 -DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00022227 -DATA 4 0x021b4818 0x00022227 - -DATA 4 0x021b083c 0x434B0350 -DATA 4 0x021b0840 0x034C0359 -DATA 4 0x021b483c 0x434B0350 -DATA 4 0x021b4840 0x03650348 -DATA 4 0x021b0848 0x4436383B -DATA 4 0x021b4848 0x39393341 -DATA 4 0x021b0850 0x35373933 -DATA 4 0x021b4850 0x48254A36 - -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F - -DATA 4 0x021b480c 0x00440044 -DATA 4 0x021b4810 0x00440044 - -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 - -DATA 4 0x021b001c 0x00000000 -DATA 4 0x021b0404 0x00011006 - -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F - -#endif /* CONFIG_MX6DQ_LPDDR2 */ diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg deleted file mode 100644 index 0d1353119ba1..000000000000 --- a/board/freescale/mx6qarm2/imximage_mx6dl.cfg +++ /dev/null @@ -1,461 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * Jason Liu r64343@freescale.com - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - - - -#ifdef CONFIG_MX6DL_LPDDR2 - -/* IOMUX SETTINGS */ -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ -DATA 4 0x020E04bc 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ -DATA 4 0x020E04c0 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */ -DATA 4 0x020E04c4 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */ -DATA 4 0x020E04c8 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */ -DATA 4 0x020E04cc 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */ -DATA 4 0x020E04d0 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */ -DATA 4 0x020E04d4 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */ -DATA 4 0x020E04d8 0x00003028 - -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ -DATA 4 0x020E0470 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ -DATA 4 0x020E0474 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */ -DATA 4 0x020E0478 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */ -DATA 4 0x020E047c 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */ -DATA 4 0x020E0480 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */ -DATA 4 0x020E0484 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */ -DATA 4 0x020E0488 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */ -DATA 4 0x020E048c 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ -DATA 4 0x020E0464 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ -DATA 4 0x020E0490 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ -DATA 4 0x020E04ac 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */ -DATA 4 0x020E04b0 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ -DATA 4 0x020E0494 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */ -DATA 4 0x020E04a4 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */ -DATA 4 0x020E04a8 0x00000038 -/* - * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - * DSE can be configured using Group Control Register: - * IOMUXC_SW_PAD_CTL_GRP_CTLDS - */ -DATA 4 0x020E04a0 0x00000000 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ -DATA 4 0x020E04b4 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ -DATA 4 0x020E04b8 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B0DS */ -DATA 4 0x020E0764 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B1DS */ -DATA 4 0x020E0770 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B2DS */ -DATA 4 0x020E0778 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B3DS */ -DATA 4 0x020E077c 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B4DS */ -DATA 4 0x020E0780 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B5DS */ -DATA 4 0x020E0784 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B6DS */ -DATA 4 0x020E078c 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B7DS */ -DATA 4 0x020E0748 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ -DATA 4 0x020E074c 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ -DATA 4 0x020E076c 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ -DATA 4 0x020E0750 0x00020000 -/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ -DATA 4 0x020E0754 0x00000000 -/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ -DATA 4 0x020E0760 0x00020000 -/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ -DATA 4 0x020E0774 0x00080000 - -/* - * DDR Controller Registers - * - * Manufacturer: Mocron - * Device Part Number: MT42L64M64D2KH-18 - * Clock Freq.: 528MHz - * MMDC channels: Both MMDC0, MMDC1 - *Density per CS in Gb: 256M - * Chip Selects used: 2 - * Number of Banks: 8 - * Row address: 14 - * Column address: 9 - * Data bus width 32 - */ - -/* MMDC_P0_BASE_ADDR = 0x021b0000 */ -/* MMDC_P1_BASE_ADDR = 0x021b4000 */ - -/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ -DATA 4 0x021b001c 0x00008000 - -/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ -DATA 4 0x021b401c 0x00008000 - -/*LPDDR2 ZQ params */ -DATA 4 0x021b085c 0x1b5f01ff -DATA 4 0x021b485c 0x1b5f01ff - -/* Calibration setup. */ -/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */ -DATA 4 0x021b0800 0xa1390003 - -/*ca bus abs delay */ -DATA 4 0x021b0890 0x00400000 -/*ca bus abs delay */ -DATA 4 0x021b4890 0x00400000 -/* values of 20,40,50,60,7f tried. no difference seen */ - -/* DDR_PHY_P1_MPWRCADL */ -DATA 4 0x021b48bc 0x00055555 - -/*frc_msr.*/ -DATA 4 0x021b08b8 0x00000800 -/*frc_msr.*/ -DATA 4 0x021b48b8 0x00000800 - -/* DDR_PHY_P0_MPREDQBY0DL3 */ -DATA 4 0x021b081c 0x33333333 -/* DDR_PHY_P0_MPREDQBY1DL3 */ -DATA 4 0x021b0820 0x33333333 -/* DDR_PHY_P0_MPREDQBY2DL3 */ -DATA 4 0x021b0824 0x33333333 -/* DDR_PHY_P0_MPREDQBY3DL3 */ -DATA 4 0x021b0828 0x33333333 -/* DDR_PHY_P1_MPREDQBY0DL3 */ -DATA 4 0x021b481c 0x33333333 -/* DDR_PHY_P1_MPREDQBY1DL3 */ -DATA 4 0x021b4820 0x33333333 -/* DDR_PHY_P1_MPREDQBY2DL3 */ -DATA 4 0x021b4824 0x33333333 -/* DDR_PHY_P1_MPREDQBY3DL3 */ -DATA 4 0x021b4828 0x33333333 - -/* - * Read and write data delay, per byte. - * For optimized DDR operation it is recommended to run mmdc_calibration - * on your board, and replace 4 delay register assigns with resulted values - * Note: - * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section - * should be skipped, or the write/read calibration comming after that - * will stall - * b. The calibration code that runs for both MMDC0 & MMDC1 should be used. - */ - -DATA 4 0x021b0848 0x4b4b524f -DATA 4 0x021b4848 0x494f4c44 - -DATA 4 0x021b0850 0x3c3d303c -DATA 4 0x021b4850 0x3c343d38 - -/*dqs gating dis */ -DATA 4 0x021b083c 0x20000000 -DATA 4 0x021b0840 0x0 -DATA 4 0x021b483c 0x20000000 -DATA 4 0x021b4840 0x0 - -/*clk delay */ -DATA 4 0x021b0858 0xa00 -/*clk delay */ -DATA 4 0x021b4858 0xa00 - -/*frc_msr */ -DATA 4 0x021b08b8 0x00000800 -/*frc_msr */ -DATA 4 0x021b48b8 0x00000800 -/* Calibration setup end */ - -/* Channel0 - startng address 0x80000000 */ -/* MMDC0_MDCFG0 */ -DATA 4 0x021b000c 0x34386145 - -/* MMDC0_MDPDC */ -DATA 4 0x021b0004 0x00020036 -/* MMDC0_MDCFG1 */ -DATA 4 0x021b0010 0x00100c83 -/* MMDC0_MDCFG2 */ -DATA 4 0x021b0014 0x000000Dc -/* MMDC0_MDMISC */ -DATA 4 0x021b0018 0x0000174C -/* MMDC0_MDRWD;*/ -DATA 4 0x021b002c 0x0f9f26d2 -/* MMDC0_MDOR */ -DATA 4 0x021b0030 0x009f0e10 -/* MMDC0_MDCFG3LP */ -DATA 4 0x021b0038 0x00190778 -/* MMDC0_MDOTC */ -DATA 4 0x021b0008 0x00000000 - -/* CS0_END */ -DATA 4 0x021b0040 0x0000005f -/* ROC */ -DATA 4 0x021b0404 0x0000000f - -/* MMDC0_MDCTL */ -DATA 4 0x021b0000 0xc3010000 - -/* Channel1 - starting address 0x10000000 */ -/* MMDC1_MDCFG0 */ -DATA 4 0x021b400c 0x34386145 - -/* MMDC1_MDPDC */ -DATA 4 0x021b4004 0x00020036 -/* MMDC1_MDCFG1 */ -DATA 4 0x021b4010 0x00100c83 -/* MMDC1_MDCFG2 */ -DATA 4 0x021b4014 0x000000Dc -/* MMDC1_MDMISC */ -DATA 4 0x021b4018 0x0000174C -/* MMDC1_MDRWD;*/ -DATA 4 0x021b402c 0x0f9f26d2 -/* MMDC1_MDOR */ -DATA 4 0x021b4030 0x009f0e10 -/* MMDC1_MDCFG3LP */ -DATA 4 0x021b4038 0x00190778 -/* MMDC1_MDOTC */ -DATA 4 0x021b4008 0x00000000 - -/* CS0_END */ -DATA 4 0x021b4040 0x0000003f - -/* MMDC1_MDCTL */ -DATA 4 0x021b4000 0xc3010000 - -/* Channel0 : Configure DDR device:*/ -/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ -DATA 4 0x021b001c 0x003f8030 -/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ -DATA 4 0x021b001c 0xff0a8030 -/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ -DATA 4 0x021b001c 0xa2018030 -/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ -DATA 4 0x021b001c 0x06028030 -/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ -DATA 4 0x021b001c 0x01038030 - -/* Channel1 : Configure DDR device:*/ -/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ -DATA 4 0x021b401c 0x003f8030 -/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ -DATA 4 0x021b401c 0xff0a8030 -/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ -DATA 4 0x021b401c 0xa2018030 -/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ -DATA 4 0x021b401c 0x06028030 -/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ -DATA 4 0x021b401c 0x01038030 - -/* MMDC0_MDREF */ -DATA 4 0x021b0020 0x00005800 -/* MMDC1_MDREF */ -DATA 4 0x021b4020 0x00005800 - -/* DDR_PHY_P0_MPODTCTRL */ -DATA 4 0x021b0818 0x0 -/* DDR_PHY_P1_MPODTCTRL */ -DATA 4 0x021b4818 0x0 - -/* - * calibration values based on calibration compare of 0x00ffff00: - * Note, these calibration values are based on Freescale's board - * May need to run calibration on target board to fine tune these - */ - -/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */ -DATA 4 0x021b0800 0xa1310003 - -/* DDR_PHY_P0_MPMUR0, frc_msr */ -DATA 4 0x021b08b8 0x00000800 -/* DDR_PHY_P1_MPMUR0, frc_msr */ -DATA 4 0x021b48b8 0x00000800 - -/* - * MMDC0_MDSCR, clear this register - * (especially the configuration bit as initialization is complete) - */ -DATA 4 0x021b001c 0x00000000 -/* - * MMDC0_MDSCR, clear this register - * (especially the configuration bit as initialization is complete) - */ -DATA 4 0x021b401c 0x00000000 - -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -DATA 4 0x020e0010 0xF00000CF -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F - -#else /* CONFIG_MX6DL_LPDDR2 */ - -DATA 4 0x020e0798 0x000c0000 -DATA 4 0x020e0758 0x00000000 -DATA 4 0x020e0588 0x00000030 -DATA 4 0x020e0594 0x00000030 -DATA 4 0x020e056c 0x00000030 -DATA 4 0x020e0578 0x00000030 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e057c 0x00000030 -DATA 4 0x020e0590 0x00003000 -DATA 4 0x020e0598 0x00003000 -DATA 4 0x020e058c 0x00000000 -DATA 4 0x020e059c 0x00003030 -DATA 4 0x020e05a0 0x00003030 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0750 0x00020000 -DATA 4 0x020e05a8 0x00000030 -DATA 4 0x020e05b0 0x00000030 -DATA 4 0x020e0524 0x00000030 -DATA 4 0x020e051c 0x00000030 -DATA 4 0x020e0518 0x00000030 -DATA 4 0x020e050c 0x00000030 -DATA 4 0x020e05b8 0x00000030 -DATA 4 0x020e05c0 0x00000030 -DATA 4 0x020e0774 0x00020000 -DATA 4 0x020e0784 0x00000030 -DATA 4 0x020e0788 0x00000030 -DATA 4 0x020e0794 0x00000030 -DATA 4 0x020e079c 0x00000030 -DATA 4 0x020e07a0 0x00000030 -DATA 4 0x020e07a4 0x00000030 -DATA 4 0x020e07a8 0x00000030 -DATA 4 0x020e0748 0x00000030 -DATA 4 0x020e05ac 0x00000030 -DATA 4 0x020e05b4 0x00000030 -DATA 4 0x020e0528 0x00000030 -DATA 4 0x020e0520 0x00000030 -DATA 4 0x020e0514 0x00000030 -DATA 4 0x020e0510 0x00000030 -DATA 4 0x020e05bc 0x00000030 -DATA 4 0x020e05c4 0x00000030 - -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b4800 0xa1390003 -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F -DATA 4 0x021b480c 0x00370037 -DATA 4 0x021b4810 0x00370037 -DATA 4 0x021b083c 0x422f0220 -DATA 4 0x021b0840 0x021f0219 -DATA 4 0x021b483C 0x422f0220 -DATA 4 0x021b4840 0x022d022f -DATA 4 0x021b0848 0x47494b49 -DATA 4 0x021b4848 0x48484c47 -DATA 4 0x021b0850 0x39382b2f -DATA 4 0x021b4850 0x2f35312c -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 -DATA 4 0x021b0004 0x0002002d -DATA 4 0x021b0008 0x00333030 - -DATA 4 0x021b000c 0x40445323 -DATA 4 0x021b0010 0xb66e8c63 - -DATA 4 0x021b0014 0x01ff00db -DATA 4 0x021b0018 0x00081740 -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b002c 0x000026d2 -DATA 4 0x021b0030 0x00440e21 -#ifdef CONFIG_DDR_32BIT -DATA 4 0x021b0040 0x00000017 -DATA 4 0x021b0000 0xc3190000 -#else -DATA 4 0x021b0040 0x00000027 -DATA 4 0x021b0000 0xc31a0000 -#endif -DATA 4 0x021b001c 0x04008032 -DATA 4 0x021b001c 0x0400803a -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x0000803b -DATA 4 0x021b001c 0x00428031 -DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x07208030 -DATA 4 0x021b001c 0x07208038 -DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b001c 0x04008048 -DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00000007 -DATA 4 0x021b4818 0x00000007 -DATA 4 0x021b0004 0x0002556d -DATA 4 0x021b4004 0x00011006 -DATA 4 0x021b001c 0x00000000 - -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -DATA 4 0x020e0010 0xF00000CF -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F -#endif /* CONFIG_MX6DL_LPDDR2 */ diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c deleted file mode 100644 index c06fd643677d..000000000000 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ /dev/null @@ -1,290 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/clock.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <usb.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -int dram_init(void) -{ -#if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \ - defined(CONFIG_DDR_32BIT) - gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2; -#else - gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; -#endif - - return 0; -} - -iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); -} - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); -} - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -int board_mmc_get_env_dev(int devno) -{ - return devno - 2; -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; - - if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(IMX_GPIO_NR(6, 11)); - ret = !gpio_get_value(IMX_GPIO_NR(6, 11)); - } else /* Don't have the CD GPIO pin on board */ - ret = 1; - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ - int ret; - u32 index = 0; - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif - -#define MII_MMD_ACCESS_CTRL_REG 0xd -#define MII_MMD_ACCESS_ADDR_DATA_REG 0xe -#define MII_DBG_PORT_REG 0x1d -#define MII_DBG_PORT2_REG 0x1e - -int fecmxc_mii_postcall(int phy) -{ - unsigned short val; - - /* - * Due to the i.MX6Q Armadillo2 board HW design,there is - * no 125Mhz clock input from SOC. In order to use RGMII, - * We need enable AR8031 ouput a 125MHz clk from CLK_25M - */ - miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7); - miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016); - miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007); - miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val); - val &= 0xffe3; - val |= 0x18; - miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val); - - /* For the RGMII phy, we need enable tx clock delay */ - miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5); - miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val); - val |= 0x0100; - miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val); - - miiphy_write("FEC", phy, MII_BMCR, 0xa100); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - struct eth_device *dev; - int ret = cpu_eth_init(bis); - - if (ret) - return ret; - - dev = eth_get_dev_by_name("FEC"); - if (!dev) { - printf("FEC MXC: Unable to get FEC device entry\n"); - return -EINVAL; - } - - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXC: Unable to register FEC mii postcall\n"); - return ret; - } - - return 0; -} - -#ifdef CONFIG_USB_EHCI_MX6 -#define USB_OTHERREGS_OFFSET 0x800 -#define UCTRL_PWR_POL (1 << 9) - -static iomux_v3_cfg_t const usb_otg_pads[] = { - MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_usb(void) -{ - imx_iomux_v3_setup_multiple_pads(usb_otg_pads, - ARRAY_SIZE(usb_otg_pads)); - - /* - * set daisy chain for otg_pin_id on 6q. - * for 6dl, this bit is reserved - */ - imx_iomux_set_gpr_register(1, 13, 1, 1); -} - -int board_ehci_hcd_init(int port) -{ - u32 *usbnc_usb_ctrl; - - if (port > 0) - return -EINVAL; - - usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + - port * 4); - - setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); - - return 0; -} -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_iomux_enet(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_USB_EHCI_MX6 - setup_usb(); -#endif - - return 0; -} - -int checkboard(void) -{ -#ifdef CONFIG_MX6DL - puts("Board: MX6DL-Armadillo2\n"); -#else - puts("Board: MX6Q-Armadillo2\n"); -#endif - - return 0; -} diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig deleted file mode 100644 index 57da844e8d3b..000000000000 --- a/configs/mx6dlarm2_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_MX6DL=y -CONFIG_TARGET_MX6QARM2=y -# CONFIG_CMD_BMODE is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,DDR_MB=2048" -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig deleted file mode 100644 index c1f4fed2cbeb..000000000000 --- a/configs/mx6dlarm2_lpddr2_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_MX6DL=y -CONFIG_TARGET_MX6QARM2=y -# CONFIG_CMD_BMODE is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL_LPDDR2,DDR_MB=512" -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig deleted file mode 100644 index 180d5f9baa69..000000000000 --- a/configs/mx6qarm2_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_MX6Q=y -CONFIG_TARGET_MX6QARM2=y -# CONFIG_CMD_BMODE is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,DDR_MB=2048" -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig deleted file mode 100644 index d481f686be02..000000000000 --- a/configs/mx6qarm2_lpddr2_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_MX6Q=y -CONFIG_TARGET_MX6QARM2=y -# CONFIG_CMD_BMODE is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6DQ_LPDDR2,DDR_MB=512" -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h deleted file mode 100644 index 83c09ead2710..000000000000 --- a/include/configs/mx6qarm2.h +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q Armadillo2 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_MXC_UART_BASE UART4_BASE - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc3\0" \ - "fdt_file=imx6q-arm2.dtb\0" \ - "fdt_addr=0x18000000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=1\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -#endif /* __CONFIG_H */