On 5/7/19 5:53 PM, Eugeniu Rosca wrote:
Hi Marek,
Hi,
Thanks for the swift reply and for the useful references/links.
On Tue, May 07, 2019 at 03:23:12PM +0200, Marek Vasut wrote:
On 5/7/19 12:41 PM, Eugeniu Rosca wrote:
Dear Marek, dear Kieran,
Hi,
[...]
1.c Use OpenOCD
- Presumably same advantages as using a Lauterbach
- Based on Kieran's https://github.com/kbingham/renesas-jtag and on Adam's https://github.com/ntfreak/openocd/commit/1afec4f561392 the solution is currently in use.
? Any ideas on the model/price of the JTAG adapter?
Any FT2232H (the H is important, due to MPSSE) works. I like Flyswatter2 from TinCanTools.
? Not tested. Any patches needed on top of vanilla OpenOCD?
http://openocd.zylin.com/5149 and related ones, it adds RPC HF support. However, there are two problems with this:
- Even with buffered write, the programming is slow
- This could be improved by running code on one of the Gen3 CPUs instead of whacking registers via JTAG adapter. I believe that's what lauterbach and everyone else does too. The data upload to SRAM/DRAM is fast via JTAG, register IO is not great.
- LifeC locks the RPC HF access
- This is a problem, since the JTAG probe cannot access it once it's locked. There might be a way around it, but it's rather nasty -- use boundary scan test mode to either flip MD pins or access the HF bus directly and bitbang at least erase command to wipe the first few sectors, then reset the CPU and have it drop to SCIF loader mode, then stop the CPU and reprogram the HF (since the SCIF loader runs in EL3 and does not touch the lifec settings.
Neither of 1) and 2) is implemented, but can be implemented if there is interest.
- looks like a performance issue to me (suboptimal flashing time).
To be honest, I don't think this is a deal-breaker, assuming that erasing/re-writing the whole 64MiB HF doesn't exceed ~10-15min. It is also my understanding this is subject of future optimization.
It will have to be optimized further.
- looks like a functional issue (insufficient permission to
write-access HF). To make things clear, could you please stress if http://openocd.zylin.com/5149 already allows updating ATF/U-Boot/OPTEE on HF of R-Car Gen3 or is it still awaiting some fixes?
You can read/write/erase the HF with it. Just keep in mind the HF has to be unlocked.
Maybe there is some magic/sectret way to unlock the LifeC RPC access restriction via JTAG, but we don't know about it.
1.d. Use CPLD Configurator
- H3_M3_StarterKit_Configurator.exe is a Windows tool shipped by Renesas, hence readily available, which allows to modify the MD pins, to conveniently switch between QSPI/Hyperflash/SCIF boot mode from a GUI
- Most of the advantages pointed out above
- ULCB-only solution (i.e. does not apply to Salvator-X)
- Requires a Windows host
Where can I obtain this and are there sources / documentation available?
I am able to find below related package freely available: https://elinux.org/File:H3_StarterKit_CPLD_Update_20190408.zip
Unfortunately, it doesn't include H3_M3_StarterKit_Configurator.exe. The user who uploaded the file is https://elinux.org/User:RenesasJa. Are you aware of any messaging/commenting feature on elinux.org? If not, I hope Michael (CC-ed) can answer your question. Hopefully he sees this message. If not, I can forward your question to him via mantis.
It would be also interesting to obtain the CPLD sources and be able to synthesise custom CPLD bitstreams for automated testing.