any feedback on the Poplar patch-set please?
On 05/29/2017 04:11 PM, Jorge Ramirez-Ortiz wrote:
Pulled from Linux 4.12-rc3
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
arch/arm/dts/hi3798cv200-poplar.dts | 162 +++++++++++++ arch/arm/dts/hi3798cv200.dtsi | 411 ++++++++++++++++++++++++++++++++ include/dt-bindings/clock/histb-clock.h | 66 +++++ include/dt-bindings/reset/ti-syscon.h | 38 +++ 4 files changed, 677 insertions(+) create mode 100644 arch/arm/dts/hi3798cv200-poplar.dts create mode 100644 arch/arm/dts/hi3798cv200.dtsi create mode 100644 include/dt-bindings/clock/histb-clock.h create mode 100644 include/dt-bindings/reset/ti-syscon.h
diff --git a/arch/arm/dts/hi3798cv200-poplar.dts b/arch/arm/dts/hi3798cv200-poplar.dts new file mode 100644 index 0000000..b914287 --- /dev/null +++ b/arch/arm/dts/hi3798cv200-poplar.dts @@ -0,0 +1,162 @@ +/*
- DTS File for HiSilicon Poplar Development Board
- Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
- Released under the GPLv2 only.
- SPDX-License-Identifier: GPL-2.0
- */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h> +#include "hi3798cv200.dtsi"
+/ {
- model = "HiSilicon Poplar Development Board";
- compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
- aliases {
serial0 = &uart0;serial2 = &uart2;- };
- chosen {
stdout-path = "serial0:115200n8";- };
- memory@0 {
device_type = "memory";reg = <0x0 0x0 0x0 0x80000000>;- };
- leds {
compatible = "gpio-leds";user-led0 {label = "USER-LED0";gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;linux,default-trigger = "heartbeat";default-state = "off";};user-led1 {label = "USER-LED1";gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;linux,default-trigger = "mmc0";default-state = "off";};user-led2 {label = "USER-LED2";gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;linux,default-trigger = "none";default-state = "off";};user-led3 {label = "USER-LED3";gpios = <&gpio10 6 GPIO_ACTIVE_LOW>;linux,default-trigger = "cpu0";default-state = "off";};- };
+};
+&gmac1 {
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- phy-handle = <ð_phy1>;
- phy-mode = "rgmii";
- hisilicon,phy-reset-delays-us = <10000 10000 30000>;
- eth_phy1: phy@3 {
reg = <3>;- };
+};
+&gpio1 {
- status = "okay";
- gpio-line-names = "LS-GPIO-E", "",
"", "","", "LS-GPIO-F","", "LS-GPIO-J";+};
+&gpio2 {
- status = "okay";
- gpio-line-names = "LS-GPIO-H", "LS-GPIO-I",
"LS-GPIO-L", "LS-GPIO-G","LS-GPIO-K", "","", "";+};
+&gpio3 {
- status = "okay";
- gpio-line-names = "", "",
"", "","LS-GPIO-C", "","", "LS-GPIO-B";+};
+&gpio4 {
- status = "okay";
- gpio-line-names = "", "",
"", "","", "LS-GPIO-D","", "";+};
+&gpio5 {
- status = "okay";
- gpio-line-names = "", "USER-LED-1",
"USER-LED-2", "","", "LS-GPIO-A","", "";+};
+&gpio6 {
- status = "okay";
- gpio-line-names = "", "",
"", "USER-LED-0","", "","", "";+};
+&gpio10 {
- status = "okay";
- gpio-line-names = "", "",
"", "","", "","USER-LED-3", "";+};
+&i2c0 {
- status = "okay";
- label = "LS-I2C0";
+};
+&i2c2 {
- status = "okay";
- label = "LS-I2C1";
+};
+&ir {
- status = "okay";
+};
+&spi0 {
- status = "okay";
- label = "LS-SPI0";
+};
+&uart0 {
- status = "okay";
+};
+&uart2 {
- status = "okay";
- label = "LS-UART0";
+}; +/* No optional LS-UART1 on Low Speed Expansion Connector. */ diff --git a/arch/arm/dts/hi3798cv200.dtsi b/arch/arm/dts/hi3798cv200.dtsi new file mode 100644 index 0000000..75865f8 --- /dev/null +++ b/arch/arm/dts/hi3798cv200.dtsi @@ -0,0 +1,411 @@ +/*
- DTS File for HiSilicon Hi3798cv200 SoC.
- Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
- Released under the GPLv2 only.
- SPDX-License-Identifier: GPL-2.0
- */
+#include <dt-bindings/clock/histb-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/ti-syscon.h>
+/ {
- compatible = "hisilicon,hi3798cv200";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- psci {
compatible = "arm,psci-0.2";method = "smc";- };
- cpus {
#address-cells = <2>;#size-cells = <0>;cpu@0 {compatible = "arm,cortex-a53";device_type = "cpu";reg = <0x0 0x0>;enable-method = "psci";};cpu@1 {compatible = "arm,cortex-a53";device_type = "cpu";reg = <0x0 0x1>;enable-method = "psci";};cpu@2 {compatible = "arm,cortex-a53";device_type = "cpu";reg = <0x0 0x2>;enable-method = "psci";};cpu@3 {compatible = "arm,cortex-a53";device_type = "cpu";reg = <0x0 0x3>;enable-method = "psci";};- };
- gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */<0x0 0xf1002000 0x0 0x100>; /* GICC */#address-cells = <0>;#interrupt-cells = <3>;interrupt-controller;- };
- timer {
compatible = "arm,armv8-timer";interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |IRQ_TYPE_LEVEL_LOW)>,<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |IRQ_TYPE_LEVEL_LOW)>,<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |IRQ_TYPE_LEVEL_LOW)>,<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |IRQ_TYPE_LEVEL_LOW)>;- };
- soc: soc@f0000000 {
compatible = "simple-bus";#address-cells = <1>;#size-cells = <1>;ranges = <0x0 0x0 0xf0000000 0x10000000>;crg: clock-reset-controller@8a22000 {compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";reg = <0x8a22000 0x1000>;#clock-cells = <1>;#reset-cells = <2>;gmacphyrst: reset-controller {compatible = "ti,syscon-reset";#reset-cells = <1>;ti,reset-bits =<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |DEASSERT_SET|STATUS_NONE)>,<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |DEASSERT_SET|STATUS_NONE)>;};};sysctrl: system-controller@8000000 {compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";reg = <0x8000000 0x1000>;#clock-cells = <1>;#reset-cells = <2>;};uart0: serial@8b00000 {compatible = "arm,pl011", "arm,primecell";reg = <0x8b00000 0x1000>;interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;clocks = <&sysctrl HISTB_UART0_CLK>;clock-names = "apb_pclk";status = "disabled";};uart2: serial@8b02000 {compatible = "arm,pl011", "arm,primecell";reg = <0x8b02000 0x1000>;interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;clocks = <&crg HISTB_UART2_CLK>;clock-names = "apb_pclk";status = "disabled";};i2c0: i2c@8b10000 {compatible = "hisilicon,hix5hd2-i2c";reg = <0x8b10000 0x1000>;#address-cells = <1>;#size-cells = <0>;interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;clock-frequency = <400000>;clocks = <&crg HISTB_I2C0_CLK>;status = "disabled";};i2c1: i2c@8b11000 {compatible = "hisilicon,hix5hd2-i2c";reg = <0x8b11000 0x1000>;#address-cells = <1>;#size-cells = <0>;interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;clock-frequency = <400000>;clocks = <&crg HISTB_I2C1_CLK>;status = "disabled";};i2c2: i2c@8b12000 {compatible = "hisilicon,hix5hd2-i2c";reg = <0x8b12000 0x1000>;#address-cells = <1>;#size-cells = <0>;interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;clock-frequency = <400000>;clocks = <&crg HISTB_I2C2_CLK>;status = "disabled";};i2c3: i2c@8b13000 {compatible = "hisilicon,hix5hd2-i2c";reg = <0x8b13000 0x1000>;#address-cells = <1>;#size-cells = <0>;interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;clock-frequency = <400000>;clocks = <&crg HISTB_I2C3_CLK>;status = "disabled";};i2c4: i2c@8b14000 {compatible = "hisilicon,hix5hd2-i2c";reg = <0x8b14000 0x1000>;#address-cells = <1>;#size-cells = <0>;interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;clock-frequency = <400000>;clocks = <&crg HISTB_I2C4_CLK>;status = "disabled";};spi0: spi@8b1a000 {compatible = "arm,pl022", "arm,primecell";reg = <0x8b1a000 0x1000>;interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;num-cs = <1>;cs-gpios = <&gpio7 1 0>;clocks = <&crg HISTB_SPI0_CLK>;clock-names = "apb_pclk";#address-cells = <1>;#size-cells = <0>;status = "disabled";};emmc: mmc@9830000 {compatible = "snps,dw-mshc";reg = <0x9830000 0x10000>;interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;clocks = <&crg HISTB_MMC_CIU_CLK>,<&crg HISTB_MMC_BIU_CLK>;clock-names = "ciu", "biu";};gpio0: gpio@8b20000 {compatible = "arm,pl061", "arm,primecell";reg = <0x8b20000 0x1000>;interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&crg HISTB_APB_CLK>;clock-names = "apb_pclk";status = "disabled";};gpio1: gpio@8b21000 {compatible = "arm,pl061", "arm,primecell";reg = <0x8b21000 0x1000>;interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&crg HISTB_APB_CLK>;clock-names = "apb_pclk";status = "disabled";};gpio2: gpio@8b22000 {compatible = "arm,pl061", "arm,primecell";reg = <0x8b22000 0x1000>;interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&crg HISTB_APB_CLK>;clock-names = "apb_pclk";status = "disabled";};gpio3: gpio@8b23000 {compatible = "arm,pl061", "arm,primecell";reg = <0x8b23000 0x1000>;interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&crg HISTB_APB_CLK>;clock-names = "apb_pclk";status = "disabled";};gpio4: gpio@8b24000 {compatible = "arm,pl061", "arm,primecell";reg = <0x8b24000 0x1000>;interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&crg HISTB_APB_CLK>;clock-names = "apb_pclk";status = "disabled";};gpio5: gpio@8004000 {compatible = "arm,pl061", "arm,primecell";reg = <0x8004000 0x1000>;interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&crg HISTB_APB_CLK>;clock-names = "apb_pclk";status = "disabled";};gpio6: gpio@8b26000 {compatible = "arm,pl061", "arm,primecell";reg = <0x8b26000 0x1000>;interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&crg HISTB_APB_CLK>;clock-names = "apb_pclk";status = "disabled";};gpio7: gpio@8b27000 {compatible = "arm,pl061", "arm,primecell";reg = <0x8b27000 0x1000>;interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&crg HISTB_APB_CLK>;clock-names = "apb_pclk";status = "disabled";};gpio8: gpio@8b28000 {compatible = "arm,pl061", "arm,primecell";reg = <0x8b28000 0x1000>;interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&crg HISTB_APB_CLK>;clock-names = "apb_pclk";status = "disabled";};gpio9: gpio@8b29000 {compatible = "arm,pl061", "arm,primecell";reg = <0x8b29000 0x1000>;interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&crg HISTB_APB_CLK>;clock-names = "apb_pclk";status = "disabled";};gpio10: gpio@8b2a000 {compatible = "arm,pl061", "arm,primecell";reg = <0x8b2a000 0x1000>;interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&crg HISTB_APB_CLK>;clock-names = "apb_pclk";status = "disabled";};gpio11: gpio@8b2b000 {compatible = "arm,pl061", "arm,primecell";reg = <0x8b2b000 0x1000>;interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&crg HISTB_APB_CLK>;clock-names = "apb_pclk";status = "disabled";};gpio12: gpio@8b2c000 {compatible = "arm,pl061", "arm,primecell";reg = <0x8b2c000 0x1000>;interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&crg HISTB_APB_CLK>;clock-names = "apb_pclk";status = "disabled";};gmac0: ethernet@9840000 {compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";reg = <0x9840000 0x1000>,<0x984300c 0x4>;interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;clocks = <&crg HISTB_ETH0_MAC_CLK>,<&crg HISTB_ETH0_MACIF_CLK>;clock-names = "mac_core", "mac_ifc";resets = <&crg 0xcc 8>,<&crg 0xcc 10>,<&gmacphyrst 0>;reset-names = "mac_core", "mac_ifc", "phy";status = "disabled";};gmac1: ethernet@9841000 {compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";reg = <0x9841000 0x1000>,<0x9843010 0x4>;interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;clocks = <&crg HISTB_ETH1_MAC_CLK>,<&crg HISTB_ETH1_MACIF_CLK>;clock-names = "mac_core", "mac_ifc";resets = <&crg 0xcc 9>,<&crg 0xcc 11>,<&gmacphyrst 1>;reset-names = "mac_core", "mac_ifc", "phy";status = "disabled";};ir: ir@8001000 {compatible = "hisilicon,hix5hd2-ir";reg = <0x8001000 0x1000>;interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;clocks = <&sysctrl HISTB_IR_CLK>;status = "disabled";};- };
+}; diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h new file mode 100644 index 0000000..181c0f0 --- /dev/null +++ b/include/dt-bindings/clock/histb-clock.h @@ -0,0 +1,66 @@ +/*
- Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program. If not, see http://www.gnu.org/licenses/.
- */
+#ifndef __DTS_HISTB_CLOCK_H +#define __DTS_HISTB_CLOCK_H
+/* clocks provided by core CRG */ +#define HISTB_OSC_CLK 0 +#define HISTB_APB_CLK 1 +#define HISTB_AHB_CLK 2 +#define HISTB_UART1_CLK 3 +#define HISTB_UART2_CLK 4 +#define HISTB_UART3_CLK 5 +#define HISTB_I2C0_CLK 6 +#define HISTB_I2C1_CLK 7 +#define HISTB_I2C2_CLK 8 +#define HISTB_I2C3_CLK 9 +#define HISTB_I2C4_CLK 10 +#define HISTB_I2C5_CLK 11 +#define HISTB_SPI0_CLK 12 +#define HISTB_SPI1_CLK 13 +#define HISTB_SPI2_CLK 14 +#define HISTB_SCI_CLK 15 +#define HISTB_FMC_CLK 16 +#define HISTB_MMC_BIU_CLK 17 +#define HISTB_MMC_CIU_CLK 18 +#define HISTB_MMC_DRV_CLK 19 +#define HISTB_MMC_SAMPLE_CLK 20 +#define HISTB_SDIO0_BIU_CLK 21 +#define HISTB_SDIO0_CIU_CLK 22 +#define HISTB_SDIO0_DRV_CLK 23 +#define HISTB_SDIO0_SAMPLE_CLK 24 +#define HISTB_PCIE_AUX_CLK 25 +#define HISTB_PCIE_PIPE_CLK 26 +#define HISTB_PCIE_SYS_CLK 27 +#define HISTB_PCIE_BUS_CLK 28 +#define HISTB_ETH0_MAC_CLK 29 +#define HISTB_ETH0_MACIF_CLK 30 +#define HISTB_ETH1_MAC_CLK 31 +#define HISTB_ETH1_MACIF_CLK 32 +#define HISTB_COMBPHY1_CLK 33
+/* clocks provided by mcu CRG */ +#define HISTB_MCE_CLK 1 +#define HISTB_IR_CLK 2 +#define HISTB_TIMER01_CLK 3 +#define HISTB_LEDC_CLK 4 +#define HISTB_UART0_CLK 5 +#define HISTB_LSADC_CLK 6
+#endif /* __DTS_HISTB_CLOCK_H */ diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h new file mode 100644 index 0000000..884fd91 --- /dev/null +++ b/include/dt-bindings/reset/ti-syscon.h @@ -0,0 +1,38 @@ +/*
- TI Syscon Reset definitions
- Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- */
+#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ +#define __DT_BINDINGS_RESET_TI_SYSCON_H__
+/*
- The reset does not support the feature and corresponding
- values are not valid
- */
+#define ASSERT_NONE (1 << 0) +#define DEASSERT_NONE (1 << 1) +#define STATUS_NONE (1 << 2)
+/* When set this function is activated by setting(vs clearing) this bit */ +#define ASSERT_SET (1 << 3) +#define DEASSERT_SET (1 << 4) +#define STATUS_SET (1 << 5)
+/* The following are the inverse of the above and are added for consistency */ +#define ASSERT_CLEAR (0 << 3) +#define DEASSERT_CLEAR (0 << 4) +#define STATUS_CLEAR (0 << 5)
+#endif