Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2.
Signed-off-by: York Sun yorksun@freescale.com Signed-off-by: Andy Fleming afleming@freescale.com
Rework L2 initialization to get all clusters
The code was double-incrementing the index, and therefore writing the wrong stash ID to the cluster. Added some comments to clarify what was happening, too.
Signed-off-by: Andy Fleming afleming@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 20 ++++++++++++++------ arch/powerpc/cpu/mpc85xx/fdt.c | 13 ++++++++++++- arch/powerpc/cpu/mpc85xx/release.S | 14 +++++++------- arch/powerpc/cpu/mpc85xx/start.S | 8 +++++--- arch/powerpc/include/asm/immap_85xx.h | 24 ++++++++++++++++++++---- 5 files changed, 58 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 1a2858a..e60129a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -309,7 +309,7 @@ static void __fsl_serdes__init(void) } __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
-#ifdef CONFIG_E6500 +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 int enable_cluster_l2(void) { int i = 0; @@ -317,13 +317,20 @@ int enable_cluster_l2(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct ccsr_cluster_l2 *l2cache;
- cluster = in_be32(&gur->tp_cluster[i++].lower); + cluster = in_be32(&gur->tp_cluster[i].lower); if (cluster & TP_CLUSTER_EOC) return 0;
+ /* The first cache has already been set up, so skip it */ + i++; + + /* Look through the remaining clusters, and set up their caches */ do { l2cache = (void *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); - cluster = in_be32(&gur->tp_cluster[i++].lower); + cluster = in_be32(&gur->tp_cluster[i].lower); + + /* set stash ID to (cluster) * 2 + 32 + 1 */ + clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
printf("enable l2 for cluster %d %p\n", i, l2cache);
@@ -331,7 +338,8 @@ int enable_cluster_l2(void) while ((in_be32(&l2cache->l2csr0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) ; out_be32(&l2cache->l2csr0, L2CSR0_L2E); - } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + i++; + } while (!(cluster & TP_CLUSTER_EOC));
return 0; } @@ -352,7 +360,7 @@ int cpu_init_r(void) #endif #ifdef CONFIG_L2_CACHE volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; -#elif defined(CONFIG_E6500) +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) struct ccsr_cluster_l2 * l2cache = (void *)CONFIG_SYS_FSL_CLUSTER_1_L2; #endif
@@ -506,7 +514,7 @@ int cpu_init_r(void) }
skip_l2: -#elif defined(CONFIG_E6500) +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) if (l2cache->l2csr0 & L2CSR0_L2E) printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 40df01c..a15e164 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -220,12 +220,18 @@ static inline void ft_fixup_l2cache(void *blob)
/* we dont bother w/L3 since no platform of this type has one */ } -#elif defined(CONFIG_BACKSIDE_L2_CACHE) +#elif defined(CONFIG_BACKSIDE_L2_CACHE) || defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) static inline void ft_fixup_l2cache(void *blob) { int off, l2_off, l3_off = -1; u32 *ph; +#ifdef CONFIG_BACKSIDE_L2_CACHE u32 l2cfg0 = mfspr(SPRN_L2CFG0); +#else + struct ccsr_cluster_l2 *l2cache = + (struct ccsr_cluster_l2 *)(CONFIG_SYS_FSL_CLUSTER_1_L2); + u32 l2cfg0 = in_be32(&l2cache->l2cfg0); +#endif u32 size, line_size, num_ways, num_sets; int has_l2 = 1;
@@ -257,7 +263,12 @@ static inline void ft_fixup_l2cache(void *blob) if (has_l2) { #ifdef CONFIG_SYS_CACHE_STASHING u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + /* Only initialize every eighth thread */ + if (reg && !((*reg) % 8)) +#else if (reg) +#endif fdt_setprop_cell(blob, l2_off, "cache-stash-id", (*reg * 2) + 32 + 1); #endif diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 22e73e0..d9061c3 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -183,13 +183,6 @@ __secondary_start_page: slwi r8,r4,5 add r10,r3,r8
-#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) - /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ - slwi r8,r4,1 - addi r8,r8,32 - mtspr L1CSR2,r8 -#endif - #ifdef CONFIG_E6500 mfspr r0,SPRN_PIR /* @@ -209,6 +202,13 @@ __secondary_start_page:
mtspr SPRN_PIR,r4 /* write to PIR register */
+#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + slwi r8,r4,1 + addi r8,r8,32 + mtspr L1CSR2,r8 +#endif + #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) /* diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 739127f..6087f62 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -169,7 +169,7 @@ l2_disabled: * */
-#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) +#ifdef CONFIG_SYS_CACHE_STASHING /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ li r2,(32 + 0) mtspr L1CSR2,r2 @@ -762,7 +762,7 @@ delete_temp_tlbs: tlbwe #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
-#ifdef CONFIG_E6500 +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 create_ccsr_l2_tlb: /* * Create a TLB for the MMR location of CCSR @@ -786,10 +786,12 @@ create_ccsr_l2_tlb: isync msync tlbwe -enable_l2_e6500: +enable_l2_cluster_l2: /* enable L2 cache */ lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l + li r4, 33 /* stash id */ + stw r4, 4(r3) lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l sync diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 62d8d0b..2a27be9 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2947,7 +2947,7 @@ typedef struct ccsr_snvs_regs { #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
-#ifdef CONFIG_E6500 +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 struct ccsr_cluster_l2 { u32 l2csr0; /* 0x000 L2 cache control and status register 0 */ u32 l2csr1; /* 0x004 L2 cache control and status register 1 */ @@ -2966,10 +2966,26 @@ struct ccsr_cluster_l2 { u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */ u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */ u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */ - u8 res_234[5]; + u8 res_234[4]; u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */ u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */ - u8 res_240[3008]; /* 0x240 - 0xdff */ + u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */ + u8 res244[4]; + u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */ + u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */ + u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */ + u8 res_254[4]; + u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */ + u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */ + u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */ + u8 res_264[4]; + u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */ + u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */ + u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */ + u8 res274[4]; + u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */ + u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */ + u8 res_280[0xb80]; /* 0x280 - 0xdff */ u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */ u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */ u32 l2errinjctl;/* 0xe08 L2 cache error injection control */ @@ -2988,5 +3004,5 @@ struct ccsr_cluster_l2 { }; #define CONFIG_SYS_FSL_CLUSTER_1_L2 \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET) -#endif /* CONFIG_E6500 */ +#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #endif /*__IMMAP_85xx__*/