From: Tom Warren twarren.nvidia@gmail.com
These files are used by both SPL and main U-Boot.
Signed-off-by: Tom Warren twarren@nvidia.com Signed-off-by: Stephen Warren swarren@nvidia.com Tested-by: Thierry Reding treding@nvidia.com --- v2: * Fixed incorrect brace placement in tegra_get_chip_sku(), and allow any SKU on Tegra124 just like other SoCs. * Simplified change to config_cache(). --- arch/arm/cpu/tegra-common/ap.c | 16 ++++++++++++---- arch/arm/cpu/tegra-common/board.c | 10 ++++++++-- arch/arm/cpu/tegra-common/cache.c | 10 ++++------ 3 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index f205be402abe..91d70da65661 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -1,5 +1,5 @@ /* -* (C) Copyright 2010-2011 +* (C) Copyright 2010-2014 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -27,7 +27,7 @@ int tegra_get_chip(void) /* * This is undocumented, Chip ID is bits 15:8 of the register * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for - * Tegra30, and 0x35 for T114. + * Tegra30, 0x35 for T114, and 0x40 for Tegra124. */ rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; debug("%s: CHIPID is 0x%02X\n", __func__, rev); @@ -84,7 +84,15 @@ int tegra_get_chip_sku(void) return TEGRA_SOC_T114; } break; + case CHIPID_TEGRA124: + switch (sku_id) { + case SKU_ID_T124_ENG: + default: + return TEGRA_SOC_T124; + } + break; } + /* unknown chip/sku id */ printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", __func__, chip_id, sku_id); @@ -119,8 +127,8 @@ static u32 get_odmdata(void) * ODMDATA is stored in the BCT in IRAM by the BootROM. * The BCT start and size are stored in the BIT in IRAM. * Read the data @ bct_start + (bct_size - 12). This works - * on T20 and T30 BCTs, which are locked down. If this changes - * in new chips (T114, etc.), we can revisit this algorithm. + * on BCTs for currently supported SoCs, which are locked down. + * If this changes in new chips, we can revisit this algorithm. */
u32 bct_start, odmdata; diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c index d9cbda8a749f..6a6faf4b2760 100644 --- a/arch/arm/cpu/tegra-common/board.c +++ b/arch/arm/cpu/tegra-common/board.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2014 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -109,12 +109,18 @@ static int uart_configs[] = { -1, -1, -1, -#else /* Tegra114 */ +#elif defined(CONFIG_TEGRA114) -1, -1, -1, FUNCMUX_UART4_GMI, /* UARTD */ -1, +#else /* Tegra124 */ + FUNCMUX_UART1_KBC, /* UARTA */ + -1, + -1, + FUNCMUX_UART4_GPIO, /* UARTD */ + -1, #endif };
diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c index 48e9319c7508..94f5bce90ec3 100644 --- a/arch/arm/cpu/tegra-common/cache.c +++ b/arch/arm/cpu/tegra-common/cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,8 +23,6 @@
void config_cache(void) { - struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; u32 reg = 0;
/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ @@ -33,10 +31,10 @@ void config_cache(void) "orr r0, r0, #0x41\n" "mcr p15, 0, r0, c1, c0, 1\n");
- /* Currently, only T114 needs this L2 cache change to boot Linux */ - reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK); - if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT)) + /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */ + if (tegra_get_chip() < CHIPID_TEGRA114) return; + /* * Systems with an architectural L2 cache must not use the PL310. * Config L2CTLR here for a data RAM latency of 3 cycles.