Dear Aaron Williams,
On 06.07.2012 01:52, Aaron Williams wrote:
Hi Zahid,
I am in charge of U-Boot for OCTEON MIPS. I have not pushed the changes back upstream since the amount of code is enormous (over 430K lines of code!). Granted, a huge percentage of that is from generated register files but it is still a huge amount of code. Just the DRAM initialization code is 9600 lines of code for DDR2 and DDR3 support.
We also do things that no other architecture does with U-Boot such as we always run in TLB mapped memory. The code is available under GPL but you need to contact support@cavium.com. With the TLB mapping it no longer matters where U-Boot is loaded in memory. The same U-Boot binary image can start executing at any 64K flash boundary in the first 4MB of flash (so we support the same image as a failsafe and standard bootloader), any 4MB boundary in RAM (when booted over PCI or eJTAG) and out of L2 cache (our top of trunk copies itself from flash to the L2 cache very early on to speed up memory initialization). The TLB mapping also allows U-Boot to be copied to the very top of memory since KSEG0 is rather limited to only 256MB. This is essential since we can support many GB of RAM which otherwise requires 64-bit addressing.
I need to push some of my changes back upstream since I have added some drivers for some temperature sensors, power monitors, fixed the AHCI driver and added a few features over the standard U-Boot (such as dynamically generated prompt support).
I would really like to see the whole stuff in mainline in favor of out of tree patches maintained only inside Cavium. Mainline U-Boot may also benefit from your generic changes and you will get reviews for free.
Best regards
Andreas Bießmann