
-----Original Message----- From: Xiaowei Bao xiaowei.bao@nxp.com Sent: 2020年3月22日 19:13 To: M.h. Lian minghuan.lian@nxp.com; Z.q. Hou zhiqiang.hou@nxp.com; Mingkai Hu mingkai.hu@nxp.com; bmeng.cn@gmail.com; yamada.masahiro@socionext.com; u-boot@lists.denx.de Cc: Xiaowei Bao xiaowei.bao@nxp.com Subject: [PATCH 8/9] pci: layerscaple: Modify the ls_pcie_dump_atu function
Modify the ls_pcie_dump_atu function, make it can print the INBOUND windows registers.
Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com
drivers/pci/pcie_layerscape.c | 25 +++++++++++++------------ drivers/pci/pcie_layerscape.h | 2 +- drivers/pci/pcie_layerscape_ep.c | 3 +++ drivers/pci/pcie_layerscape_rc.c | 2 +- 4 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index c7a96ed..4015a0d 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -117,24 +117,25 @@ void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag, PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2); }
-void ls_pcie_dump_atu(struct ls_pcie *pcie) +void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type) {
- int i;
- int win_idx;
- for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
PCIE_ATU_VIEWPORT);
debug("iATU%d:\n", i);
- for (win_idx = 0; win_idx < win_num; win_idx++) {
dbi_writel(pcie, type | win_idx, PCIE_ATU_VIEWPORT);
debug("\tLOWER PHYS 0x%08x\n", dbi_readl(pcie, PCIE_ATU_LOWER_BASE)); debug("\tUPPER PHYS 0x%08x\n", dbi_readl(pcie, PCIE_ATU_UPPER_BASE));debug("iATU%d:\n", win_idx);
debug("\tLOWER BUS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
debug("\tUPPER BUS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
debug("\tLIMIT 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_LIMIT));
if (type == PCIE_ATU_REGION_OUTBOUND) {
debug("\tLOWER BUS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
debug("\tUPPER BUS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
debug("\tLIMIT 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_LIMIT));
debug("\tCR1 0x%08x\n", dbi_readl(pcie, PCIE_ATU_CR1)); debug("\tCR2 0x%08x\n",}
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 26d0177..5f5c51d 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -185,7 +185,7 @@ void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type, u64 phys, u64 bus_addr, u64 size); void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag, int type, int idx, int bar, u64 phys); -void ls_pcie_dump_atu(struct ls_pcie *pcie); +void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type); int ls_pcie_link_up(struct ls_pcie *pcie); void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie); void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie); diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index 67ce36c..ebf69ee 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -226,6 +226,9 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep) ls_pcie_ep_setup_atu(pcie_ep, 0); }
- ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM_SRIOV,
PCIE_ATU_REGION_INBOUND);
- ls_pcie_ep_enable_cfg(pcie_ep);
}
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c index 927722d..b045159 100644 --- a/drivers/pci/pcie_layerscape_rc.c +++ b/drivers/pci/pcie_layerscape_rc.c @@ -114,7 +114,7 @@ static void ls_pcie_setup_atu(struct ls_pcie_rc *pcie_rc) pref->bus_start, pref->size);
- ls_pcie_dump_atu(pcie);
- ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM,
PCIE_ATU_REGION_OUTBOUND); }
/* Return 0 if the address is valid, -errno if not valid */
2.9.5
Reviewed-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com