Hi Mark,
On Mon, 11 Sept 2023 at 14:25, Mark Kettenis mark.kettenis@xs4all.nl wrote:
From: Simon Glass sjg@google.com Date: Sun, 10 Sep 2023 16:36:48 -0600
Hi,
On Wed, 6 Sept 2023 at 15:50, Janne Grunau j@jannau.net wrote:
Apple's M2 Ultra SoC are somewhat similar to the M1 Ultra but needs a tweaked memory map as the M2 Pro/Max SoCs. USB, NVMe, UART, WDT and PCIe are working with the existing drivers.
Signed-off-by: Janne Grunau j@jannau.net
arch/arm/mach-apple/board.c | 183 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+)
diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index d50194811843..47393babbc62 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -444,6 +444,187 @@ static struct mm_region t6020_mem_map[] = { } };
+/* Apple M2 Ultra */
+static struct mm_region t6022_mem_map[] = {
{/* I/O */.virt = 0x280000000,.phys = 0x280000000,.size = SZ_1G,.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |PTE_BLOCK_NON_SHARE |PTE_BLOCK_PXN | PTE_BLOCK_UXN}, {Is there no devicetree binding for this information?
Not directly. The device tree does contain the addresses of the devices of course. But what we want here is a memory map that uses a few big ranges that cover all the devices in the device tree rather than lots of small ranges that cover the individual devices.
OK I see.
But yes, it sucks that every time Apple produces a new SoC we need to add another memory map.
Regards, Simon