From: Xu Jiucheng B37781@freescale.com
When P1021RDB-PC reboot system, the board will hung at uboot DDR configuration. For P1021RDB-PC DDR reset pin is multiplex with QE, so uboot will reserve this pin for QE and skip DDR reset. Other platforms without QE will do this reset. This patch adds a slight code to reset DDR chip by QE CE_PB8 pin for NAND and NOR FLASH boot. For booting from SPI FALSH and SD card, it seems possible to use the rom on chip to write to the GPIO pins before configuring the DDR.
Signed-off-by: Xu Jiucheng B37781@freescale.com Signed-off-by: Xie Xiaobo X.Xie@freescale.com --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 19 ++++++++++++++++++- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 15 +++++++++++++++ 2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index ef62638..2e0e0c7 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -55,6 +55,13 @@ #define GPIO_SLIC_PIN 30 #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
+#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) +#define GPIO_DDR_RST_PORT 1 +#define GPIO_DDR_RST_PIN 8 +#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN)) + +#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2)) +#endif
#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB) #define PCA_IOPORT_I2C_ADDR 0x23 @@ -67,7 +74,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* GPIO */ {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */ -#if 0 +#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */ #endif {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */ @@ -159,6 +166,16 @@ void board_gpio_init(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
+#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) + /* reset DDR3 */ + setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); + udelay(1000); + clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); + udelay(1000); + setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); + /* disable CE_PB8 */ + clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK); +#endif /* Enable VSC7385 switch */ setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index 09019e9..e2bfb0d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -81,6 +81,8 @@ void board_init_f(ulong bootflag) ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; #ifndef CONFIG_QE ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); +#elif defined(CONFIG_P1021RDB) + par_io_t *par_io = (par_io_t *)&(gur->qe_par_io); #endif
/* initialize selected port with appropriate baud rate */ @@ -102,6 +104,19 @@ void board_init_f(ulong bootflag) __raw_writel(0x00200000, &pgpio->gpdat); udelay(1000); __raw_writel(0x00000000, &pgpio->gpdir); +#elif defined(CONFIG_P1021RDB) + /* init DDR3 reset signal CE_PB8 */ + out_be32(&par_io[1].cpdir1, 0x00004000); + out_be32(&par_io[1].cpodr, 0x00800000); + out_be32(&par_io[1].cppar1, 0x00000000); + /* reset DDR3 */ + out_be32(&par_io[1].cpdat, 0x00800000); + udelay(1000); + out_be32(&par_io[1].cpdat, 0x00000000); + udelay(1000); + out_be32(&par_io[1].cpdat, 0x00800000); + /* disable the CE_PB8 */ + out_be32(&par_io[1].cpdir1, 0x00000000); #endif
#ifndef CONFIG_SYS_INIT_L2_ADDR