Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

Hi,

On Tuesday 03 October 2017 05:34 PM, Marek Vasut wrote:

On 09/19/2017 01:15 PM, Faiz Abbas wrote:

...

A flush of the cache is required before any DMA access can take place.

You mean invalidation for inbound DMA, flush for outbound DMA, right ?

yes thats what i meant.

...

• dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));

• dwc3_flush_cache((uintptr_t)dwc->ep0_trb_addr, sizeof(*trb) * 2);

Why *2 ?

Because its allocated as sizeof(*dwc->ep0_trb) * 2 below. This is not strictly required as dwc3_flush_cache() rounds up the size to CACHELINE_SIZE but from a caller POV, flush everything we allocated.

Thanks, Faiz