On Wednesday, December 16, 2015 at 05:28:48 PM, Eric Nelson wrote:
Hi Marek,
Hi!
On 12/16/2015 08:33 AM, Marek Vasut wrote:
On Wednesday, December 16, 2015 at 04:00:38 PM, Eric Nelson wrote:
Hi Marek,
On 12/16/2015 07:40 AM, Marek Vasut wrote:
Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code fine-tunes the behavior of the MMDC controller in order to improve the signal integrity and memory stability.
I'm glad to see that others are interested in this.
I've been working on something similar, but struggling to have time
to finish and clean it up: https://github.com/ericnelsonaz/u-boot/tree/memcal-pass1
My aim is/was a bit different though, and aims to be a replacement for the DDR stress tool, which is cumbersome to use.
Excellent, we can add this as an optional feature or something which can be triggered by command, since the "full" calibration takes some time.
To do that, I put together a pseudo-board with Kconfig options for the serial console, memory bus width, and such.
Or maybe this can be built as a mutated SPL ?
That's how I have things hacked together. The board "mx6memcal" essentially **only** produces SPL.
It runs calibration, then spits out the results in a form usable by either a .cfg file or SPL data structure.
I'd like to add a trailing memory test with frequency walking as done with the DDR stress tool before submitting it though.
Gotcha! That'd be great thing to have %^)
Signed-off-by: Marek Vasut marex@denx.de Cc: Stefano Babic sbabic@denx.de
arch/arm/cpu/armv7/mx6/ddr.c | 559 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/mx6-ddr.h | 5 + 2 files changed, 564 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 6b039e4..194411f 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -13,6 +13,565 @@
#include <asm/io.h> #include <asm/types.h>
I'll review this in detail later, but off-hand, I think this could use a new CONFIG_ variable to exclude it from boards that don't use it.
It also shouldn't be difficult to support i.MX6SL and LPDDR here.
This is OK, the code will be compiled for these MX6 variants, but it will be dropped from the final binary if you don't call it explicitly (see patch 2/2).
Gotcha.
I don't have SX/SL, so I couldn't test it there.
I have a couple of SL boards, so I can do that (mx6slevk and a custom board using DDR3). Both of them support SPL, so it shouldn't take long to validate.
Excellent! Let's do this as a subsequent patch though, since this code is actually tested extensively and I'd like to keep it as a reference for possible bisecting ;-)