Hi Simon,
On Tue, Feb 21, 2023 at 3:49 AM Simon Glass sjg@chromium.org wrote:
Pick this up from the sysinfo tables and display it with the cbsysinfo command. This allows the 'acpi list' command to work when booting from coreboot.
Signed-off-by: Simon Glass sjg@chromium.org
arch/x86/include/asm/cb_sysinfo.h | 2 ++ arch/x86/include/asm/coreboot_tables.h | 2 ++ arch/x86/lib/coreboot/cb_sysinfo.c | 11 +++++++++++ cmd/x86/cbsysinfo.c | 1 + 4 files changed, 16 insertions(+)
diff --git a/arch/x86/include/asm/cb_sysinfo.h b/arch/x86/include/asm/cb_sysinfo.h index 0201ac6b03a..6b266149cf6 100644 --- a/arch/x86/include/asm/cb_sysinfo.h +++ b/arch/x86/include/asm/cb_sysinfo.h @@ -133,6 +133,7 @@
- @mtc_size: Size of MTC region
- @chromeos_vpd: Chromium OS Vital Product Data region, typically NULL, meaning
not used
*/
- @rsdp: Pointer to ACPI RSDP table
struct sysinfo_t { unsigned int cpu_khz; @@ -211,6 +212,7 @@ struct sysinfo_t { u64 mtc_start; u32 mtc_size; void *chromeos_vpd;
void *rsdp;};
extern struct sysinfo_t lib_sysinfo; diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index f131de56a40..2d6f3db3a5f 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -422,6 +422,8 @@ struct cb_tsc_info { #define CB_TAG_SERIALNO 0x002a #define CB_MAX_SERIALNO_LENGTH 32
+#define CB_TAG_ACPI_RSDP 0x0043
This is using space but should be tab.
#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
struct cb_cmos_option_table { diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c b/arch/x86/lib/coreboot/cb_sysinfo.c index 748fa4ee53b..a11a2587f66 100644 --- a/arch/x86/lib/coreboot/cb_sysinfo.c +++ b/arch/x86/lib/coreboot/cb_sysinfo.c @@ -264,6 +264,13 @@ static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info) info->mrc_cache = map_sysmem(cbmem->cbmem_tab, 0); }
+static void cb_parse_acpi_rsdp(void *ptr, struct sysinfo_t *info) +{
struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr;info->rsdp = map_sysmem(cbmem->cbmem_tab, 0);+}
__weak void cb_parse_unhandled(u32 tag, unsigned char *ptr) { } @@ -428,6 +435,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_MRC_CACHE: cb_parse_mrc_cache(rec, info); break;
case CB_TAG_ACPI_RSDP:cb_parse_acpi_rsdp(rec, info);break; default: cb_parse_unhandled(rec->tag, ptr); break;@@ -454,6 +464,7 @@ int get_coreboot_info(struct sysinfo_t *info) if (!ret) return -ENOENT; gd->arch.coreboot_table = addr;
gd_set_acpi_start(map_to_sysmem(info->rsdp)); gd->flags |= GD_FLG_SKIP_LL_INIT; return 0;diff --git a/cmd/x86/cbsysinfo.c b/cmd/x86/cbsysinfo.c index 34fdaf5b1b1..07570b00c9a 100644 --- a/cmd/x86/cbsysinfo.c +++ b/cmd/x86/cbsysinfo.c @@ -363,6 +363,7 @@ static void show_table(struct sysinfo_t *info, bool verbose) print_hex("MTC size", info->mtc_size);
print_ptr("Chrome OS VPD", info->chromeos_vpd);
print_ptr("RSDP", info->rsdp);}
static int do_cbsysinfo(struct cmd_tbl *cmdtp, int flag, int argc,
I tested this patch on top of coreboot with U-Boot as a payload running on QEMU i440fx, but U-Boot does not list acpi tables.
=> acpi list No ACPI tables present
Regards, Bin