Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree.
On x86 it doesn't make a lot of sense to have a separate SPL device tree. Since everything is in the same ROM we might as well just use the main device tree in both SPL and U-Boot proper. But we haven't implemented that, so this is a good first step.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v3: - Expand pre-reloc malloc() size in this patch to prevent boot failure
Changes in v2: None
arch/x86/dts/chromebook_link.dts | 15 ++++++++++++++- configs/chromebook_link_defconfig | 4 ++-- 2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index b93234046e0..fab919a3589 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -26,12 +26,14 @@ cpus { #address-cells = <1>; #size-cells = <0>; + u-boot,dm-pre-reloc;
cpu@0 { device_type = "cpu"; compatible = "intel,core-gen3"; reg = <0>; intel,apic-id = <0>; + u-boot,dm-pre-reloc; };
cpu@1 { @@ -39,6 +41,7 @@ compatible = "intel,core-gen3"; reg = <1>; intel,apic-id = <1>; + u-boot,dm-pre-reloc; };
cpu@2 { @@ -46,6 +49,7 @@ compatible = "intel,core-gen3"; reg = <2>; intel,apic-id = <2>; + u-boot,dm-pre-reloc; };
cpu@3 { @@ -53,6 +57,7 @@ compatible = "intel,core-gen3"; reg = <3>; intel,apic-id = <3>; + u-boot,dm-pre-reloc; };
}; @@ -229,14 +234,16 @@
northbridge@0,0 { reg = <0x00000000 0 0 0 0>; + u-boot,dm-pre-reloc; compatible = "intel,bd82x6x-northbridge"; board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>, <&gpio_b 11 0>, <&gpio_a 10 0>; - u-boot,dm-pre-reloc; spd { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <0>; elpida_4Gb_1600_x16 { + u-boot,dm-pre-reloc; reg = <0>; data = [92 10 0b 03 04 19 02 02 03 52 01 08 0a 00 fe 00 @@ -272,6 +279,7 @@ 00 00 00 00 00 00 00 00]; }; samsung_4Gb_1600_1.35v_x16 { + u-boot,dm-pre-reloc; reg = <1>; data = [92 11 0b 03 04 19 02 02 03 11 01 08 0a 00 fe 00 @@ -391,9 +399,11 @@ #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich9-spi"; + u-boot,dm-pre-reloc; spi-flash@0 { #size-cells = <1>; #address-cells = <1>; + u-boot,dm-pre-reloc; reg = <0>; compatible = "winbond,w25q64", "spi-flash"; @@ -401,6 +411,7 @@ rw-mrc-cache { label = "rw-mrc-cache"; reg = <0x003e0000 0x00010000>; + u-boot,dm-pre-reloc; }; }; }; @@ -478,7 +489,9 @@ };
microcode { + u-boot,dm-pre-reloc; update@0 { + u-boot,dm-pre-reloc; #include "microcode/m12306a9_0000001b.dtsi" }; }; diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 84077312c37..bf3795f13ce 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -1,5 +1,5 @@ CONFIG_X86=y -CONFIG_SYS_MALLOC_F_LEN=0x1800 +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_VENDOR_GOOGLE=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" CONFIG_TARGET_CHROMEBOOK_LINK=y @@ -57,8 +57,8 @@ CONFIG_TPM_TIS_LPC=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y +CONFIG_USB_KEYBOARD=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y