On 3/22/19 9:30 AM, Marek Vasut wrote:
Pull the PL310 clearing code into common code, so it can be reused by Arria10.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dalon Westergreen dwesterg@gmail.com Cc: Dinh Nguyen dinguyen@kernel.org
arch/arm/mach-socfpga/include/mach/misc.h | 1 + arch/arm/mach-socfpga/misc.c | 54 +++++++++++++++++++++++ arch/arm/mach-socfpga/spl_gen5.c | 54 ----------------------- 3 files changed, 55 insertions(+), 54 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 86d5d2b62b..876b850be2 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void); #endif
void do_bridge_reset(int enable); +void socfpga_pl310_clear(void);
#endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index ec8339e045..14337ff2d9 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -46,6 +46,60 @@ int dram_init(void) return 0; }
+void socfpga_pl310_clear(void) +{
- u32 mask = 0xff, ena = 0;
- icache_enable();
- /* Disable the L2 cache */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
- writel(0x0, &pl310->pl310_tag_latency_ctrl);
- writel(0x10, &pl310->pl310_data_latency_ctrl);
- /* enable BRESP, instruction and data prefetch, full line of zeroes */
- setbits_le32(&pl310->pl310_aux_ctrl,
L310_AUX_CTRL_DATA_PREFETCH_MASK |L310_AUX_CTRL_INST_PREFETCH_MASK |L310_SHARED_ATT_OVERRIDE_ENABLE);
Do we need to enable these bits here? They get enabled again in v7_outer_cache_enable().
Otherwise, feel free to add:
Reviewed-by: Dinh Nguyen dinguyen@kernel.org
Dinh