This was discussed in the list a while ago but a patch was not submitted AFAIK. I've come up with a patch that does not break any existing boards and naming of the macro is in line with other U-Boot macros for similar settings.
Re: http://sf.net/mailarchive/message.php?msg_id=14093274 Re: http://sf.net/mailarchive/message.php?msg_id=14095552
I am currently involved with bring-up of an 405EP based board. For our board we do actually need CPC0_PCI[SPE] set to "1" to configure PerWE*/PCI_INT* as PerWE* so write cycles to our flash could be take place (even for just CFI detection)
CHANGELOG:
* (ppc405ep) Add support for board configuration of CPC0_PCI register This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE*
Sign-off-by: Tolunay Orkun listmember@orkun.us
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 948de43..316285a 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1526,7 +1526,8 @@ ppc405ep_init: mtdcr ebccfgd,r3 #endif
- addi r3,0,CPC0_PCI_HOST_CFG_EN +#ifndef CFG_CPC0_PCI + li r3,CPC0_PCI_HOST_CFG_EN #ifdef CONFIG_BUBINGA /* !----------------------------------------------------------------------- @@ -1541,6 +1542,9 @@ ppc405ep_init: beq ..pci_cfg_set /* if not set, then bypass reg write*/ #endif ori r3,r3,CPC0_PCI_ARBIT_EN +#else + li r3,CFG_CPC0_PCI +#endif ..pci_cfg_set: mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/