Hi Jason,
On Tue, 2 Jun 2020 at 19:55, Jason Li jason.li@cortina-access.com wrote:
Hi Miquel/Tom,
Hi Alex,
Alex Nemirovsky alex.nemirovsky@cortina-access.com wrote on Mon, 1 Jun 2020 14:26:49 -0700:
From: Jason Li jason.li@cortina-access.com
Supports all CAxxxx SoCs which support a parallel nand controller. It should be noted that some CAxxxx Soc also support an separate SPI serial NAND controller.
This driver only supports the parallel NAND controller. A different driver supports the SPI NAND interface controller.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
CC: Miquel Raynal miquel.raynal@bootlin.com CC: Simon Glass sjg@chromium.org CC: Tom Rini trini@konsulko.com
Changes in v3:
- Include udelay.h to avoid implicit declaration of udelay()
Changes in v2:
- Cleanup code style to pass checkpatch.pl
MAINTAINERS | 2 + drivers/mtd/nand/raw/Kconfig | 31 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/ca_nand.c | 4943 ++++++++++++++++++++++++++++++++++++++++ drivers/mtd/nand/raw/ca_nand.h | 3899 +++++++++++++++++++++++++++++++
This is insanely big !
5 files changed, 8876 insertions(+) create mode 100644 drivers/mtd/nand/raw/ca_nand.c create mode 100644 drivers/mtd/nand/raw/ca_nand.h
diff --git a/MAINTAINERS b/MAINTAINERS index 8add9d4..6da2ad8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -181,6 +181,8 @@ F: drivers/gpio/cortina_gpio.c F: drivers/watchdog/cortina_wdt.c F: drivers/serial/serial_cortina.c F: drivers/mmc/ca_dw_mmc.c +F: drivers/mtd/nand/raw/ca_nand.c +F: drivers/mtd/nand/raw/ca_nand.h
ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun marek.behun@nic.cz diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index c4d9d31..b3cbfcc 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -102,6 +102,37 @@ config NAND_BRCMNAND_63158 help Enable support for broadcom nand driver on bcm63158.
+config NAND_CORTINA
tristate "Support Cortina-Access Parallel NAND cntlr."- select SYS_NAND_SELF_INIT
Alignment looks wrong
helpThis enables the parallel RAW NAND driver for the- Cortina-Access CAxxxx Family of SoCs.
+config NAND_CORTINA_ECC_LEVEL
int "Cortina-Access Parallel Nand driver HW ECC algorithm"default 3range 0 5depends on NAND_CORTINAhelpNAND Flash ECC algorithm. Value range from 0 to 5.The default value is 3.0: Hamming algorithm. Correct 3 bad bits in 256 btyes.1: Hamming algorithm. Correct 3 bad bits in 512 btyes.2: BCH algorithm. Correct 8 bad bits in 1K btyes.3: BCH algorithm. Correct 16 bad bits in 1K btyes.4: BCH algorithm. Correct 24 bad bits in 1K btyes.5: BCH algorithm. Correct 40 bad bits in 1K btyes.Not sure how u-boot guys want to handle this but the current way to request for a specif correction is to pass nand-ecc-strength and nand-ecc-size DT properties. If the driver does not support the requested properties, there is a function (at least in Linux) which finds the closest correction called nand_ecc_choose_conf(), provided that you implemented a few specific hooks in your driver.
We have drivers making use of those properties too, so this one should as well. Thanks!
-- Tom
Since DTB is separate image from u-boot. If we put these information in DTB. What ECC algorithm should be applied when read DTB from flash? Could you guide more detail.
Typically DTB is packaged with U-Boot and they are loaded together. So they should use the same ECC algorithm.
If you have a complicated image, take a look at binman.
Regards, Simon