Some Exynos SoCs (not supported by pinctrl-exynos driver yet) have different offsets and widths of pin bank registers (i.e. PIN_CON, PIN_PUD and PIN_DRV registers). Rework pinctrl-exynos driver so it allows for different offsets and widths of those registers by adding the corresponding API. That makes it possible to add the support for new Exynos SoCs in pinctrl-exynos driver.
The main patch in this series is:
pinctrl: exynos: Support different register types in pin banks
Other patches are just related cleanups and refactoring commits, required for the clean implementation of the main patch.
Sam Protsenko (7): pinctrl: exynos: Improve coding style pinctrl: exynos: Extract pin parsing code into a separate function pinctrl: exynos: Rework pin_to_bank_base() to obtain data by name pinctrl: exynos: Support different register types in pin banks pinctrl: exynos: Refactor handling the pin related dt properties pinctrl: exynos: Reduce variables scope pinctrl: exynos: Convert to use livetree API for fdt access
drivers/pinctrl/exynos/pinctrl-exynos.c | 125 ++++++++++++-------- drivers/pinctrl/exynos/pinctrl-exynos.h | 36 +++++- drivers/pinctrl/exynos/pinctrl-exynos7420.c | 2 + 3 files changed, 108 insertions(+), 55 deletions(-)