From: Joe Xue lgxue@hotmail.com
--- README | 7 + drivers/net/Makefile | 1 + drivers/net/ax88183.c | 265 +++++++++++++++++++++++ drivers/net/ax88183.h | 559 +++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 832 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ax88183.c create mode 100644 drivers/net/ax88183.h
diff --git a/README b/README index 68f5fb0..e389ec5 100644 --- a/README +++ b/README @@ -876,6 +876,13 @@ The following options need to be configured: automatically converts one 32 bit word to two 16 bit words you may also try CONFIG_SMC911X_32_BIT.
+ CONFIG_DRIVER_AX88183 + Support for AXIS's AX88183 chips. + + CONFIG_AX88183_BASE + Define this to hold the physical address + of the AX88183's I/O space + - USB Support: At the moment only the UHCI host controller is supported (PIP405, MIP405, MPC5200); define diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b605eea..ab15d46 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -83,6 +83,7 @@ COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o COBJS-$(CONFIG_ULI526X) += uli526x.o COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o +COBJS-$(CONFIG_DRIVER_AX88183) += ax88183.o
COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/ax88183.c b/drivers/net/ax88183.c new file mode 100644 index 0000000..ed41244 --- /dev/null +++ b/drivers/net/ax88183.c @@ -0,0 +1,265 @@ + +/* + * (C) Copyright 2010 Joe Xue lgxue@hotmail.com + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. +*/ + +/* + * This driver works on 32bit mode + * AX88783 has two ethernet ports, we only use port 0 in u-boot + */ + +#include <common.h> +#include <command.h> +#include <net.h> +#include <linux/mii.h> +#include <miiphy.h> +#include <config.h> +#include "ax88183.h" + +static int ax88183_init(bd_t *bd) +{ + volatile unsigned int tmp; + int i; + + /* reset chip */ + tmp = CR; + CR = (tmp & ~CR_CHIP_RESET); + udelay(1000); + CR = (tmp | CR_CHIP_RESET); + + /* disable interrupt */ + IMSR = IMSR_MASK_ALL; + + /* set mac address*/ + unsigned char mactmp[4]; + unsigned int * mac = (unsigned int *)mactmp; + mactmp[0] = bd->bi_enetaddr[5]; + mactmp[1] = bd->bi_enetaddr[4]; + mactmp[2] = bd->bi_enetaddr[3]; + mactmp[3] = bd->bi_enetaddr[2]; + P0MAC0 = *mac; + + mactmp[0] = bd->bi_enetaddr[1]; + mactmp[1] = bd->bi_enetaddr[0]; + P0MAC1 = *mac; + + /* write mac to forward entry */ + mactmp[0] = bd->bi_enetaddr[3]; + mactmp[1] = bd->bi_enetaddr[2]; + mactmp[2] = bd->bi_enetaddr[1]; + mactmp[3] = bd->bi_enetaddr[0]; + FTDATA = *mac; + FTCMD = bd->bi_enetaddr[4] | (bd->bi_enetaddr[5]<<8) | \ + FTCMD_FT_PORT(0x2) | FTCMD_FT_STATIC | \ + FTCMD_WRITE_FT; + + /* phy init */ + tmp = PCR; + tmp |= PCR_PHY0_RESET_CLEAR; + PCR = tmp; + udelay(100000); + tmp = POLLCR; + tmp &= POLLCR_PORT0_PHYID_MASK; + tmp |= POLLCR_PORT0_PHYID(0x10); + POLLCR = tmp; + + /* write MII mode */ + tmp = (MIICR & 0xFF); + tmp &= (~MIICR_PORT0_MII_CLK_GEN); + tmp &= (~MIICR_PORT0_PHY_RMII); + MIICR = tmp; + + /* set LED mode */ + tmp = LEDCR; + tmp |= LEDCR_PORT_LED_ON(0) | LEDCR_LED0(PHY_LED_RX | PHY_LED_TX); + tmp |= LEDCR_PORT_LED_ON(1) | LEDCR_LED1(PHY_LED_LINK); + LEDCR= tmp; + + /* set auto polling */ + tmp = POLLCR; + tmp |= (POLLCR_PORT0_AUTO_POOLING); + POLLCR = tmp; + + /* set link speed */ + for(i=0 ;i<2; i++) + { + int reg = i*8+16; + tmp = MDCR_READ | MDCR_PHY_ID(0x10) | MDCR_PHY_REG(reg); + MDCR = tmp; + while(1) + { + tmp = MDCR; + if(tmp & MDCR_VALID) + break; + } + tmp = MDCR & MDCR_VALUE_MASK; + + tmp = tmp | 0x1000 | MDCR_WRITE | MDCR_PHY_ID(0x10) | MDCR_PHY_REG(reg); + MDCR = tmp; + while(1) + { + tmp = MDCR; + if(tmp & MDCR_VALID) + break; + } + } + + /* media init */ + tmp = MDCR_READ | MDCR_PHY_ID(0x10) | MDCR_PHY_REG(MII_ADVERTISE); + MDCR = tmp; + while(1) + { + tmp = MDCR; + if(tmp & MDCR_VALID) + break; + } + + tmp = MDCR & MDCR_VALUE_MASK; + tmp &= (~ADVERTISE_ALL); + tmp |= ADVERTISE_ALL | 0x400; + tmp = tmp | MDCR_WRITE | MDCR_PHY_ID(0x10); + MDCR = tmp; + while(1) + { + tmp = MDCR; + if(tmp & MDCR_VALID) + break; + } + + tmp = MDCR_WRITE | MDCR_PHY_ID(0x10) | MDCR_PHY_REG(MII_BMCR)| BMCR_ANRESTART | BMCR_ANENABLE; + MDCR = tmp; + while(1) + { + tmp = MDCR; + if(tmp & MDCR_VALID) + break; + } + + /* packet order */ + BORDER = BORDER_LITTLE; + + /* local bus cpi */ + tmp = L2PSR; + tmp |= L2PSR_CPIO_ON; + L2PSR = tmp; + return 0; + +} + + +void eth_halt (void) +{ + ; +} + +int eth_init (bd_t * bd) +{ + + char *s, *e; + int i; + + s = getenv ("ethaddr"); + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + +#if 0 + printf ("\tHW MAC address: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + bd->bi_enetaddr[0], bd->bi_enetaddr[1], + bd->bi_enetaddr[2], bd->bi_enetaddr[3], + bd->bi_enetaddr[4], bd->bi_enetaddr[5] ); +#endif + + return ax88183_init(bd); +} + +/* Get a data block via Ethernet */ +int eth_rx (void) +{ + unsigned long length, reverse_length; + volatile unsigned int tmp; + unsigned int i; + + tmp = IMSR; + while(tmp & IMSR_INT_CPO_EMPTY) + { + IMSR = IMSR; + CSCR = CSCR_CPO_START; + tmp = DATAPORT; + + tmp = ((tmp & 0xFF000000) >> 24 ) | + ( (tmp & 0x00FF0000) >> 8 ) | + ( (tmp & 0x0000FF00) << 8 ) | + ( (tmp & 0x000000FF) << 24 ); + + if(tmp == 0) + continue; + + length = tmp & 0xffff; + reverse_length = (~(tmp>>16))&0xffff; + if(length != reverse_length) + { + /* reset CPO */ + tmp = CR; + tmp &= ~CR_CPO_RESET; + CR = tmp; + continue; + } + + length = length & 0x7ff; + + /* align the length */ + length = ((length+3)/4)*4; + + char *buf = NetRxPackets[0]; + for(i=0; i<length; i+=4) + { + tmp = DATAPORT; + buf[i] = (unsigned char)(tmp & 0xff); + buf[i+1] = (unsigned char)((tmp >> 8) & 0xff); + buf[i+2] = (unsigned char)((tmp >> 16) & 0xff); + buf[i+3] = (unsigned char)((tmp >> 24) & 0xff); + } + + /* pass to up level */ + NetReceive(NetRxPackets[0], (unsigned short) length); + + tmp = IMSR; + } + return (int) length; +} + +/* Send a data block via Ethernet. */ +int eth_send (volatile void *packet, int length) +{ + unsigned int pkt_header, tmp, i; + unsigned char *buf = (unsigned char *)packet; + + tmp = length; + tmp = (~tmp<<16) | tmp; + pkt_header = ((tmp & 0xff000000) >> 24) | \ + ((tmp & 0x00ff0000) >> 8) | \ + ((tmp & 0x0000ff00) << 8) | \ + ((tmp & 0x000000ff) << 24); + + CSCR = CSCR_CPI_START; + DATAPORT = pkt_header; + + for(i=0; i<length; i+=4) + { + tmp = (unsigned int)*(buf + i) | \ + (((unsigned int)*(buf + i + 1)) << 8) | \ + (((unsigned int)*(buf + i + 2)) << 16) | \ + (((unsigned int)*(buf + i + 3)) << 24); + DATAPORT = tmp; + } + + return 0; +} + diff --git a/drivers/net/ax88183.h b/drivers/net/ax88183.h new file mode 100644 index 0000000..fa70eac --- /dev/null +++ b/drivers/net/ax88183.h @@ -0,0 +1,559 @@ + +/* + * (C) Copyright 2010 Joe Xue lgxue@hotmail.com + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. +*/ + +#ifndef __AX88183_H__ +#define __AX88183_H__ + +#include <config.h> + +/* + *------------------------------------------------------------------------- + * Registers + *------------------------------------------------------------------------- + */ + +#define CR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0000)) + #define CR_CHIP_MODE_8BIT (0) + #define CR_CHIP_MODE_16BIT (1) + #define CR_CHIP_MODE_32BIT (2) + #define CR_CHIP_MODE_SPI (3) + #define CR_CHIP_MODE_PCI (4) + #define CR_CHIP_MODE_MASK (0x07) + #define CR_CHIP_REVISION_MASK (0x0F00) + #define CR_CHIP_INIT_DONE (1 << 16) + #define CR_CPI_RESET (1 << 26) + #define CR_CPO_RESET (1 << 27) + #define CR_SWITCH_CORE_RESET (1 << 28) + #define CR_CHIP_RESET (1 << 31) + +#define PCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0004)) + #define PCR_PHY0_RESET_CLEAR (1) + #define PCR_PHY1_RESET_CLEAR (0x00010000) + +#define PSR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0008)) + +#define GMCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x000c)) + #define GMCR_MPL(Length) (Longth & 0x7FF) + #define GMCR_NO_ABORT (1 << 13) + #define GMCR_MAX_STORM(Mode) ((Mode & 0x03) << 14) + #define GMCR_SUPER_MAC (1 << 21) + #define GMCR_PTO (1 << 22) + #define GMCR_CSJ (1 << 23) + #define GMCR_GEN_CRC (1 << 26) + #define GMCR_INT_ACTIVE_HIGH (1 << 27) + #define GMCR_INT_ACTIVE_LOW (0) + #define GMCR_INS_SRC_FROM_CPU (1 << 28) + #define GMCR_INS_SRC_TO_CPU (1 << 29) + #define GMCR_PCI_FIFO_ON (1 << 31) + +#define L2PSR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0010)) + #define L2PSR_DIFF_SEL (1 << 0) + #define L2PSR_COS_ON (1 << 1) + #define L2PSR_TOS_ON (1 << 2) + #define L2PSR_DSCP_ON (1 << 3) + #define L2PSR_FILTER_MAC (1 << 4) + #define L2PSR_STOP_LEARNING (1 << 5) + #define L2PSR_ARP_TO_CPU (1 << 6) + #define L2PSR_HASH_MODE_LINEAR (0) + #define L2PSR_HASH_MODE_HASH (1 << 7) + #define L2PSR_CPIO_ON (1 << 9) + #define L2PSR_MC_OVER_VLAN (1 << 10) + #define L2PSR_CTRL_PKT_TO_CPU (1 << 12) + #define L2PSR_IGMP_ON (1 << 13) + #define L2PSR_IGMP_FORWARD_TO_CPU (1 << 14) + #define L2PSR_IGMP_COPY_TO_CPU (0) + #define L2PSR_QINQ_ON (1 << 15) + #define L2PSR_1X_ON (1 << 16) + #define L2PSR_GMRP_ON (1 << 17) + #define L2PSR_GVRP_ON (1 << 18) + #define L2PSR_GARP_ON (1 << 19) + #define L2PSR_VALN_ON (1 << 20) + #define L2PSR_1P_ON (1 << 21) + #define L22PSR_1Q_ON (1 << 22) + #define L2PSR_1D_ON (1 << 23) + +#define L2FCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0014)) + #define L2FCR_BROADCAST_ON(Port) (1 << (Port)) + #define L2FCR_FLOOD_ON(Port) (1 <<((Port) + 4)) + #define L2FCR_MULTICAST_ON(Port) (1 <<((Port) + 8)) + #define L2FCR_LEARNING_ON(Port) (1 << (12 + (Port))) + #define L2FCR_AGING_TIME(Time) ((Time) << 16) + #define L2FCR_ONE_SA_RESET(Port) (1 << (26 + (Port))) + #define L2FCR_ONE_SA_ON (1 << (29 + (Port))) + +#define FTDATA (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0018)) + +#define FTCMD (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x001c)) + #define FTCMD_WRITE_FT (1 << 31) + #define FTCMD_READ_FT (1 << 30) + #define FTCMD_FLUSH_FT (1 << 29) + #define FTCMD_SER_BYPORT (1 << 28) + #define FTCMD_CONTI_FT (1 << 27) + #define FTCMD_FT_PAGE0 (0) + #define FTCMD_FT_PAGE1 (1 << 26) + #define FTCMD_FT_PAGE(x) (x << 26) + #define FTCMD_FT_END (1 << 25) + #define FTCMD_FT_VALID (1 << 24) + #define FTCMD_FT_PORT1 (1 << 23) + #define FTCMD_FT_PORT0 (1 << 22) + #define FTCMD_FT_FLUSH_DOWN (1 << 21) + #define FTCMD_FT_STATIC (1 << 20) + #define FTCMD_FT_FILTER_DA (1 << 19) + #define FTCMD_FT_FILTER_SA (1 << 18) + #define FTCMD_FT_PORT(x) (x << 16) + +#define QDCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0020)) + #define QDCR_PORT_STATE(Port, State) (State << (Port * 2)) + #define QDCR_VLAN_FILTER_ON(Port) (1 << (8 + Port)) + #define QDCR_VLAN_PORT_MAP(Group, Map) (Map << (16 + Group * 4)) + +#define SCR0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0024)) + +#define SCR1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0028)) + +#define SCR2 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x002c)) + +#define PMTR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0030)) + #define PMTR_PRIORITY_MASK (0x03) + #define PMTR_TOS_MASK (0x0000FFFF) + #define PMTR_COS_MASK (0xFFFF0000) + +#define DQCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0034)) + +#define PRCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0038)) + +#define MDCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x003c)) + #define MDCR_WRITE (1 << 31) + #define MDCR_READ (1 << 30) + #define MDCR_VALID (1 << 29) + #define MDCR_PHY_ID(x) (x << 24) + #define MDCR_PHY_REG(x) (x << 16) + #define MDCR_VALUE_MASK (0xFFFF) + +#define TOCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0040)) + #define TOCR_INJECT_UDP_CKECKSUM (1 << 0) + #define TOCR_INJECT_TCP_CKECKSUM (1 << 1) + #define TOCR_INJECT_IGMP_CKECKSUM (1 << 2) + #define TOCR_INJECT_ICMP_CKECKSUM (1 << 3) + #define TOCR_INJECT_IP_CKECKSUM (1 << 4) + #define TOCR_INJECT_PPPOE_CKECKSUM (1 << 5) + #define TOCR_DROP_ERR_UDP_CHECKSUM (1 << 8) + #define TOCR_DROP_ERR_TCP_CHECKSUM (1 << 9) + #define TOCR_DROP_ERR_IGMP_CHECKSUM (1 << 10) + #define TOCR_DROP_ERR_ICMP_CHECKSUM (1 << 11) + #define TOCR_DROP_ERR_IP_CHECKSUM (1 << 12) + #define TOCR_DROP_ERR_PPPOE_CHECKSUM (1 << 13) + +#define DATAPORT (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x004c)) + #define CPI_INSERT_PORT_ON (1 << 15) + #define CPI_INSERT_PORT_NUM(x) ((unsigned short)(x) << 13) + #define CPO_PORT_NUM(x) ((unsigned char)((x) >> 15)) + +#define SMAC0DATA (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0050)) + +#define SMAC0CR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0054)) + #define SMACCR_SRC_PORT(Port) ((Port & 0x03) << 16) + #define SMACCR_GET_SRC_PORT(x) ((unsigned char)((x >> 16) & 0x03)) + #define SMACCR_SNIFFER_SA (1 << 18) + #define SMACCR_SNIFFER_DA (1 << 19) + #define SMACCR_SNIFFER_PAIR (1 << 20) + #define SMACCR_1X_SA_MATCH (1 << 27) + #define SMACCR_FILTER_PAIR (1 << 28) + #define SMACCR_FILTER_SA (1 << 29) + #define SMACCR_FILTER_DA (1 << 30) + #define SMACCR_FORWARDING_ON (1 << 31) + +#define SMAC1DATA (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0058)) + +#define SMAC1CR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x005c)) + +#define SMAC2DATA (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0060)) + +#define SMAC2CR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0064)) + +#define SMAC3DATA (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0068)) + +#define SMAC3CR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x006C)) + +#define SMAC4DATA (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0070)) + +#define SMAC4CR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0074)) + +#define SMAC5DATA (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0078)) + +#define SMAC5CR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x007C)) + +#define SMAC6DATA (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0080)) + +#define SMAC6CR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0084)) + +#define SMAC7DATA (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0088)) + +#define SMAC8CR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x008C)) + +#define VENTRY0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0090)) + #define VENTRY_MEMBER_PORT0 (1) + #define VENTRY_MEMBER_PORT1 (1 << 1) + #define VENTRY_MEMBER_PORT2 (1 << 2) + #define VENTRY_OUTPUT_TAG_PORT0 (1 << 3) + #define VENTRY_OUTPUT_TAG_PORT1 (1 << 4) + #define VENTRY_OUTPUT_TAG_PORT2 (1 << 5) + #define VENTRY_VLANID_MASK (0xFFFC003F) + #define VENTRY_VLANID(Reg) ((unsigned short)((Reg >> 6) & 0xFFF)) + #define VENTRY_VALID (1 << 18) + +#define VENTRY1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0094)) + +#define VENTRY2 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0098)) + +#define VENTRY3 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x009c)) + +#define VENTRY4 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00A0)) + +#define VENTRY5 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00A4)) + +#define VENTRY6 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00A8)) + +#define VENTRY7 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00AC)) + +#define VENTRY8 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00B0)) + +#define VENTRY9 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00B4)) + +#define VENTRY10 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00B8)) + +#define VENTRY11 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00BC)) + +#define VENTRY12 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00C0)) + +#define VENTRY13 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00C4)) + +#define VENTRY14 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00C8)) + +#define VENTRY15 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00CC)) + +#define BORDER (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00D0)) + #define BORDER_BIG (0) + #define BORDER_LITTLE (1) + #define BORDER_PCI (1 << 2) + +#define CSCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00D4)) + #define CSCR_CPI_START (1 << 15) + #define CSCR_CPO_START (1 << 31) + +#define MULTCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00D8)) + +#define LEDCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00DC)) + #define LEDCR_LED0(x) (x) + #define LEDCR_LED1(x) (x << 8) + #define LEDCR_LED2(x) (x << 16) + #define LEDCR_PORT_LED_ON(Port) (1 << (24 + Port)) + #define PHY_LED_SPEED (1 << 0) + #define PHY_LED_DUPLEX (1 << 1) + #define PHY_LED_LINK (1 << 2) + #define PHY_LED_RX (1 << 3) + #define PHY_LED_TX (1 << 4) + #define PHY_LED_COLLISION (1 << 5) + +#define RMONCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00E0)) + #define RMONCR_CLEAR (1 << 4) + #define RMONCR_PORT(Port) (Port << 13) + #define RMONCR_RMON_ADDR(x) (x << 8) + #define RMONCR_READ (1 << 15) + +#define RMONDR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00E4)) + +#define DSCPTBL0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00E8)) + +#define DSCPTBL1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00EC)) + +#define DSCPTBL2 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00F0)) + +#define DSCPTBL3 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00F4)) + +#define IMSR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00F8)) + #define IMSR_INT_AGAIN (1 << 0) + #define IMSR_INT_NEW_LEARN (1 << 1) + #define IMSR_INT_CPI_ERR (1 << 2) + #define IMSR_INT_CPO_EMPTY (1 << 3) + #define IMSR_INT_CPI_FULL (1 << 4) + #define IMSR_INT_CPI_CLEAR (1 << 5) + #define IMSR_INT_LINK_CHANGE (1 << 6) + #define IMSR_INT_PCI_RX (1 << 7) + #define IMSR_INT_PCI_TX (1 << 8) + #define IMSR_INT_PCI_RX_HALT (1 << 9) + #define IMSR_INT_PCI_TX_HALT (1 << 10) + #define IMSR_INT_TIMER (1 << 11) + + #define IMSR_MASK_AGAIN (1 << 16) + #define IMSR_MASK_NEW_LEARN (1 << 17) + #define IMSR_MASK_CPI_ERR (1 << 18) + #define IMSR_MASK_CPO_EMPTY (1 << 19) + #define IMSR_MASK_CPI_FULL (1 << 20) + #define IMSR_MASK_CPI_CLEAR (1 << 21) + #define IMSR_MASK_LINK_CHANGE (1 << 22) + #define IMSR_MASK_PCI_RX (1 << 23) + #define IMSR_MASK_PCI_TX (1 << 24) + #define IMSR_MASK_PCI_RX_HALT (1 << 25) + #define IMSR_MASK_PCI_TX_HALT (1 << 26) + #define IMSR_MASK_TIMER (1 << 27) + #define IMSR_MASK_ALL 0xFFFF0000 + +#define PCDR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x00FC)) + +#define SUDPTCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0100)) + +#define WOLCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0104)) + #define WOLCR_PORT0_LINK_CHANGE (1 << 0) + #define WOLCR_PORT0_MAGIC_PACKET (1 << 1) + #define WOLCR_PORT0_WAKEUP_FRAME (1 << 2) + #define WOLCR_PORT0_CASCADE0 (1 << 3) + #define WOLCR_PORT0_CASCADE1 (1 << 4) + #define WOLCR_PORT1_LINK_CHANGE (1 << 5) + #define WOLCR_PORT1_MAGIC_PACKET (1 << 6) + #define WOLCR_PORT1_WAKEUP_FRAME (1 << 7) + #define WOLCR_PORT1_CASCADE0 (1 << 8) + #define WOLCR_PORT1_CASCADE1 (1 << 9) + #define WOLCR_WAKEUP_START (1 << 16) + #define WOLCR_SLEEP_START (1 << 17) + #define WOLCR_WAKEUP_CLEAR (1 << 18) + #define WOLCR_SLEEP_CLEAR (1 << 19) + #define WOLCR_PORT0_WAKEUP (1 << 29) + #define WOLCR_PORT1_WAKEUP (1 << 30) + +#define WOLSR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0108)) + #define WOLSR_PORT0_OFFSET0(x) (x) + #define WOLSR_PORT0_OFFSET0_MASK (0x0000000F) + #define WOLSR_PORT0_OFFSET1(x) (x << 4) + #define WOLSR_PORT0_OFFSET1_MASK (0x000000F0) + #define WOLSR_PORT0_OFFSET2(x) (x << 8) + #define WOLSR_PORT0_OFFSET2_MASK (0x00000F00) + #define WOLSR_PORT0_MASK0_ON (1 << 12) + #define WOLSR_PORT0_MASK1_ON (1 << 13) + #define WOLSR_PORT0_MASK2_ON (1 << 14) + #define WOLSR_PORT0_DA_MATCH (1 << 15) + + #define WOLSR_PORT1_OFFSET0(x) (x << 16) + #define WOLSR_PORT1_OFFSET0_MASK (0x000F0000) + #define WOLSR_PORT1_OFFSET1(x) (x << 20) + #define WOLSR_PORT1_OFFSET1_MASK (0x00F00000) + #define WOLSR_PORT1_OFFSET2(x) (x << 24) + #define WOLSR_PORT1_OFFSET2_MASK (0x0F000000) + #define WOLSR_PORT1_MASK0_ON (1 << 28) + #define WOLSR_PORT1_MASK1_ON (1 << 29) + #define WOLSR_PORT1_MASK2_ON (1 << 30) + #define WOLSR_PORT1_DA_MATCH (1 << 31) + +#define PORT0MASK0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x010C)) + +#define PORT0MASK1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0110)) + +#define PORT0MASK2 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0114)) + +#define PORT0CRC0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0118)) + +#define PORT0CRC1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x011C)) + +#define PORT0CRC2 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0120)) + +#define PORT1MASK0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0124)) + +#define PORT1MASK1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0128)) + +#define PORT1MASK2 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x012C)) + +#define PORT1CRC0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0130)) + +#define PORT1CRC1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0134)) + +#define PORT1CRC2 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0138)) + +#define POLLCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0140)) + #define POLLCR_PORT0_PHYID_MASK (0xFFFFFFE0) + #define POLLCR_PORT0_PHYID(x) (x) + #define POLLCR_PORT1_PHYID_MASK (0xFFFFE0FF) + #define POLLCR_PORT1_PHYID(x) (x << 8) + #define POLLCR_PORT2_PHYID_MASK (0xFFE0FFFF) + #define POLLCR_PORT2_PHYID(x) (x << 16) + #define POLLCR_PORT0_AUTO_POOLING 0x11000000 + #define POLLCR_PORT0_AUTO_POOLING_MASK 0xEEFFFFFF + #define POLLCR_PORT1_AUTO_POOLING 0x22000000 + #define POLLCR_PORT1_AUTO_POOLING_MASK 0xDDFFFFFF + #define POLLCR_PORT2_AUTO_POOLING 0x44000000 + #define POLLCR_PORT2_AUTO_POOLING_MASK 0xBBFFFFFF + +#define EECR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0144)) + #define EECR_CHK (1 << 24) + #define EECR_MODE(x) (x << 27) + #define EECR_VALID (1 << 30) + #define EECR_REQ (1 << 31) + #define EECR_ADDR(x) (x << 8) + +#define BLCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0148)) + #define BLCR_DONE (1 << 30) + #define BLCR_RELOAD (1 << 31) + +#define IGENTRY0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0150)) + +#define IGENTRY1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0154)) + +#define IGENTRY2 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0158)) + +#define IGENTRY3 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x015C)) + +#define IGENTRY4 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0160)) + +#define IGENTRY5 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0164)) + +#define IGENTRY6 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0168)) + +#define IGENTRY7 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x016C)) + +#define MULTIFILTER (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x01B0)) + +#define MIICR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x01F0)) + #define MIICR_PORT0_MII_CLK_GEN (1 << 0) + #define MIICR_PORT1_MII_CLK_GEN (1 << 1) + #define MIICR_PORT2_MII_CLK_GEN (1 << 2) + #define MIICR_PORT0_PHY_RMII (1 << 4) + #define MIICR_PORT1_PHY_RMII (1 << 5) + #define MIICR_PORT2_PHY_RMII (1 << 6) + +#define CSLEEPCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x01F4)) + +#define ENDIANCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x01F8)) + +#define TIMERCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x01FC)) + +#define P0MCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0200)) + #define MCR_MAC_ON (1 << 0) + #define MCR_SPEED100 (1 << 3) + #define MCR_DUPLEX_FULL (1 << 4) + #define MCR_FLOWCTRL_ON (1 << 7) + #define MCR_CRC_CHECK (1 << 8) + #define MCR_ACCEPT_ALL (1 << 10) + #define MCR_MCR_RX_STOP (1 << 12) + #define MCR_MCR_TX_STOP (1 << 13) + #define MCR_RX_RATE_ON (1 << 16) + #define MCR_TX_RATE_ON (1 << 17) + #define MCR_DA_MATCH (1 << 18) + #define MCR_UniRxStart (MCR_FLOWCTRL_ON | MCR_CRC_CHECK | MCR_DA_MATCH) + #define MCR_PromisRxStart (MCR_FLOWCTRL_ON | MCR_CRC_CHECK) + #define MCR_MAC_STOP (0) + +#define P0QMTBL (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0204)) + #define QMTBL_PRIORITY_MASK (0x03) + #define QMTBL_REMAP_MASK (0x07) + #define QMTBL_TX_ON (1 << 31) + +#define P0QSR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0208)) + #define QSR_GET_PVID(x) ((unsigned short)((x) & 0xFFF)) + #define QSR_PVID_MASK (0xFFFFF000) + #define QSR_PRIORITY_MASK (0xFFFF1FFF) + #define QSR_SET_PRIORITY(Pri) (((unsigned long)(Pri)) << 13) + #define QSR_GET_PRIORITY(Reg) ((unsigned char)(((Reg) >> 13) & 0x07)) + +#define P0RQRL0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x020C)) + +#define P0RQRL1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0210)) + +#define P0TQRL0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0214)) + +#define P0TQRL1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0218)) + +#define P0RL (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x021C)) + #define P0RL_TX_RATE_MASK 0x0000FFFF + #define P0RL_RX_RATE_MASK 0xFFFF0000 + +#define P0CTSR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0220)) + +#define P0WATERMARK (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0224)) + +#define P0BMU (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0228)) + #define BMU_QUEUE_MASK(queue) (0x000F << (4*queue)) + +#define P0RXDROP (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x022C)) + +#define P0MAC0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0230)) + +#define P0MAC1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0234)) + +#define P1MCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0240)) + +#define P1QMTBL (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0244)) + +#define P1QSR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0248)) + +#define P1RQRL0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x024C)) + +#define P1RQRL1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0250)) + +#define P1TQRL0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0254)) + +#define P1TQRL1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0258)) + +#define P1RL (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x025C)) + +#define P1CTSR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0260)) + +#define P1WATERMARK (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0264)) + +#define P1BMU (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0268)) + +#define P1RXDROP (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x026C)) + +#define P1MAC0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0270)) + +#define P1MAC1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0274)) + +#define P2MCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0280)) + +#define P2QMTBL (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0284)) + +#define P2QSR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0288)) + +#define P2RQRL0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x028C)) + +#define P2RQRL1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0290)) + +#define P2TQRL0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0294)) + +#define P2TQRL1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x0298)) + +#define P2RL (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x029C)) + +#define P2CTSR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x02A0)) + +#define P2WATERMARK (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x02A4)) + +#define P2BMU (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x02A8)) + +#define P2RXDROP (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x02AC)) + +#define P2MAC0 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x02B0)) + +#define P2MAC1 (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x02B4)) + +#define DMARXCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x02C0)) + #define DMACR_START (1 << 31) + #define DMACR_RELOAD (1 << 30) + #define DMACR_STOP (1 << 29) + #define DMACR_PKT_NBUSY (1 << 2) + #define DMACR_IDLE (1 << 0) + +#define DMARXDESCPA (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x02C4)) + +#define DMATXCR (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x02C8)) + +#define DMATXDESCPA (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x02CC)) + +#define DMAHWTX (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x02D0)) + +#define DMAHWRX (*(volatile unsigned int *)(CONFIG_AX88183_BASE + 0x02D4)) + +#endif