2013/1/16 Gabor Juhos juhosg@openwrt.org:
The romReserved and romExcHandle handlers are accessed by a branch instruction however the delay slots of those instructions are not filled.
Because the start.S uses the 'noreorder' directive, the assembler will not fill the delay slots either, and leads to the following assembly code:
0000056c <romReserved>: 56c: 1000ffff b 56c <romReserved>
00000570 <romExcHandle>: 570: 1000ffff b 570 <romExcHandle>
In the resulting code, the second branch instruction is placed into the delay slot of the first branch instruction, which is not allowed on the MIPS architecture.
Signed-off-by: Gabor Juhos juhosg@openwrt.org Cc: Daniel Schwierzeck daniel.schwierzeck@googlemail.com
arch/mips/cpu/mips32/start.S | 2 ++ arch/mips/cpu/mips64/start.S | 1 + 2 files changed, 3 insertions(+)
applied to u-boot-mips/master, thanks