From: Peng Fan peng.fan@nxp.com
Add SCFW macro definition.
Signed-off-by: Peng Fan peng.fan@nxp.com Reviewed-by: Anatolij Gustschin agust@denx.de Cc: Stefano Babic sbabic@denx.de --- arch/arm/include/asm/arch-imx8/sci/rpc.h | 158 +++++++++++++ arch/arm/include/asm/arch-imx8/sci/sci.h | 58 +++++ .../include/asm/arch-imx8/sci/svc/misc/api.h | 30 +++ .../include/asm/arch-imx8/sci/svc/pad/api.h | 57 +++++ .../include/asm/arch-imx8/sci/svc/pm/api.h | 44 ++++ .../include/asm/arch-imx8/sci/svc/rm/api.h | 69 ++++++ arch/arm/include/asm/arch-imx8/sci/types.h | 220 ++++++++++++++++++ 7 files changed, 636 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/sci/rpc.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/types.h
diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h new file mode 100644 index 0000000000..746c2fa24d --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2018 NXP + * + */ + +#ifndef SC_RPC_H +#define SC_RPC_H + +/* Note: Check SCFW API Released DOC before you want to modify something */ +#define SC_RPC_VERSION 1U + +#define SC_RPC_MAX_MSG 8U + +#define RPC_VER(MSG) ((MSG)->version) +#define RPC_SIZE(MSG) ((MSG)->size) +#define RPC_SVC(MSG) ((MSG)->svc) +#define RPC_FUNC(MSG) ((MSG)->func) +#define RPC_R8(MSG) ((MSG)->func) +#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U]) +#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U]) +#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)]) +#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U]) +#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U]) +#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)]) + +#define SC_RPC_SVC_UNKNOWN 0U +#define SC_RPC_SVC_RETURN 1U +#define SC_RPC_SVC_PM 2U +#define SC_RPC_SVC_RM 3U +#define SC_RPC_SVC_TIMER 5U +#define SC_RPC_SVC_PAD 6U +#define SC_RPC_SVC_MISC 7U +#define SC_RPC_SVC_IRQ 8U +#define SC_RPC_SVC_ABORT 9U + +/* Types */ + +struct sc_rpc_msg_s { + u8 version; + u8 size; + u8 svc; + u8 func; + union { + s32 i32[(SC_RPC_MAX_MSG - 1U)]; + s16 i16[(SC_RPC_MAX_MSG - 1U) * 2U]; + s8 i8[(SC_RPC_MAX_MSG - 1U) * 4U]; + u32 u32[(SC_RPC_MAX_MSG - 1U)]; + u16 u16[(SC_RPC_MAX_MSG - 1U) * 2U]; + u8 u8[(SC_RPC_MAX_MSG - 1U) * 4U]; + } DATA; +}; + +/* PM RPC */ +#define PM_FUNC_UNKNOWN 0 +#define PM_FUNC_SET_SYS_POWER_MODE 19U +#define PM_FUNC_SET_PARTITION_POWER_MODE 1U +#define PM_FUNC_GET_SYS_POWER_MODE 2U +#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U +#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U +#define PM_FUNC_REQ_LOW_POWER_MODE 16U +#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U +#define PM_FUNC_SET_CPU_RESUME_ADDR 17U +#define PM_FUNC_SET_CPU_RESUME 21U +#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U +#define PM_FUNC_SET_CLOCK_RATE 5U +#define PM_FUNC_GET_CLOCK_RATE 6U +#define PM_FUNC_CLOCK_ENABLE 7U +#define PM_FUNC_SET_CLOCK_PARENT 14U +#define PM_FUNC_GET_CLOCK_PARENT 15U +#define PM_FUNC_RESET 13U +#define PM_FUNC_RESET_REASON 10U +#define PM_FUNC_BOOT 8U +#define PM_FUNC_REBOOT 9U +#define PM_FUNC_REBOOT_PARTITION 12U +#define PM_FUNC_CPU_START 11U + +/* MISC RPC */ +#define MISC_FUNC_UNKNOWN 0 +#define MISC_FUNC_SET_CONTROL 1U +#define MISC_FUNC_GET_CONTROL 2U +#define MISC_FUNC_SET_MAX_DMA_GROUP 4U +#define MISC_FUNC_SET_DMA_GROUP 5U +#define MISC_FUNC_SECO_IMAGE_LOAD 8U +#define MISC_FUNC_SECO_AUTHENTICATE 9U +#define MISC_FUNC_SECO_FUSE_WRITE 20U +#define MISC_FUNC_SECO_ENABLE_DEBUG 21U +#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U +#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U +#define MISC_FUNC_SECO_BUILD_INFO 24U +#define MISC_FUNC_DEBUG_OUT 10U +#define MISC_FUNC_WAVEFORM_CAPTURE 6U +#define MISC_FUNC_BUILD_INFO 15U +#define MISC_FUNC_UNIQUE_ID 19U +#define MISC_FUNC_SET_ARI 3U +#define MISC_FUNC_BOOT_STATUS 7U +#define MISC_FUNC_BOOT_DONE 14U +#define MISC_FUNC_OTP_FUSE_READ 11U +#define MISC_FUNC_OTP_FUSE_WRITE 17U +#define MISC_FUNC_SET_TEMP 12U +#define MISC_FUNC_GET_TEMP 13U +#define MISC_FUNC_GET_BOOT_DEV 16U +#define MISC_FUNC_GET_BUTTON_STATUS 18U + +/* PAD RPC */ +#define PAD_FUNC_UNKNOWN 0 +#define PAD_FUNC_SET_MUX 1U +#define PAD_FUNC_GET_MUX 6U +#define PAD_FUNC_SET_GP 2U +#define PAD_FUNC_GET_GP 7U +#define PAD_FUNC_SET_WAKEUP 4U +#define PAD_FUNC_GET_WAKEUP 9U +#define PAD_FUNC_SET_ALL 5U +#define PAD_FUNC_GET_ALL 10U +#define PAD_FUNC_SET 15U +#define PAD_FUNC_GET 16U +#define PAD_FUNC_SET_GP_28FDSOI 11U +#define PAD_FUNC_GET_GP_28FDSOI 12U +#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U +#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U +#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U +#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U + +/* RM RPC */ +#define RM_FUNC_UNKNOWN 0 +#define RM_FUNC_PARTITION_ALLOC 1U +#define RM_FUNC_SET_CONFIDENTIAL 31U +#define RM_FUNC_PARTITION_FREE 2U +#define RM_FUNC_GET_DID 26U +#define RM_FUNC_PARTITION_STATIC 3U +#define RM_FUNC_PARTITION_LOCK 4U +#define RM_FUNC_GET_PARTITION 5U +#define RM_FUNC_SET_PARENT 6U +#define RM_FUNC_MOVE_ALL 7U +#define RM_FUNC_ASSIGN_RESOURCE 8U +#define RM_FUNC_SET_RESOURCE_MOVABLE 9U +#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U +#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U +#define RM_FUNC_SET_MASTER_SID 11U +#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U +#define RM_FUNC_IS_RESOURCE_OWNED 13U +#define RM_FUNC_IS_RESOURCE_MASTER 14U +#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U +#define RM_FUNC_GET_RESOURCE_INFO 16U +#define RM_FUNC_MEMREG_ALLOC 17U +#define RM_FUNC_MEMREG_SPLIT 29U +#define RM_FUNC_MEMREG_FREE 18U +#define RM_FUNC_FIND_MEMREG 30U +#define RM_FUNC_ASSIGN_MEMREG 19U +#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U +#define RM_FUNC_IS_MEMREG_OWNED 21U +#define RM_FUNC_GET_MEMREG_INFO 22U +#define RM_FUNC_ASSIGN_PAD 23U +#define RM_FUNC_SET_PAD_MOVABLE 24U +#define RM_FUNC_IS_PAD_OWNED 25U +#define RM_FUNC_DUMP 27U + +#endif /* SC_RPC_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h new file mode 100644 index 0000000000..d0ff5c5c41 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _SC_SCI_H +#define _SC_SCI_H + +#include <asm/arch/sci/types.h> +#include <asm/arch/sci/svc/misc/api.h> +#include <asm/arch/sci/svc/pad/api.h> +#include <asm/arch/sci/svc/pm/api.h> +#include <asm/arch/sci/svc/rm/api.h> +#include <asm/arch/sci/rpc.h> +#include <dt-bindings/soc/imx_rsrc.h> +#include <linux/errno.h> + +static inline int sc_err_to_linux(sc_err_t err) +{ + int ret; + + switch (err) { + case SC_ERR_NONE: + return 0; + case SC_ERR_VERSION: + case SC_ERR_CONFIG: + case SC_ERR_PARM: + ret = -EINVAL; + break; + case SC_ERR_NOACCESS: + case SC_ERR_LOCKED: + case SC_ERR_UNAVAILABLE: + ret = -EACCES; + break; + case SC_ERR_NOTFOUND: + case SC_ERR_NOPOWER: + ret = -ENODEV; + break; + case SC_ERR_IPC: + ret = -EIO; + break; + case SC_ERR_BUSY: + ret = -EBUSY; + break; + case SC_ERR_FAIL: + ret = -EIO; + break; + default: + ret = 0; + break; + } + + debug("%s %d %d\n", __func__, err, ret); + + return ret; +} + +#endif diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h new file mode 100644 index 0000000000..5d17b553d7 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_MISC_API_H +#define SC_MISC_API_H + +/* Defines for sc_misc_boot_status_t */ +#define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */ +#define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */ + +/* Defines for sc_misc_seco_auth_cmd_t */ +#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */ + +/* Defines for sc_misc_temp_t */ +#define SC_MISC_TEMP 0U /* Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ + +/* Defines for sc_misc_seco_auth_cmd_t */ +#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */ +#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */ +#define SC_MISC_REL_CONTAINER 2U /* Release container */ + +typedef u8 sc_misc_boot_status_t; + +#endif /* SC_MISC_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h new file mode 100644 index 0000000000..905c56834e --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_PAD_API_H +#define SC_PAD_API_H + +/* Defines for sc_pad_config_t */ +#define SC_PAD_CONFIG_NORMAL 0U /* Normal */ +#define SC_PAD_CONFIG_OD 1U /* Open Drain */ +#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */ +#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */ + +/* Defines for sc_pad_iso_t */ +#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */ +#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */ +#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */ +#define SC_PAD_ISO_ON 3U /* ISO latched data is held */ + +/* Defines for sc_pad_28fdsoi_dse_t */ +#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed for 1.8v */ +#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength dual volt */ +#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength dual volt */ + +/* Defines for sc_pad_28fdsoi_ps_t */ +#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */ +#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */ +#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */ +#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */ + +/* Defines for sc_pad_28fdsoi_pus_t */ +#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */ +#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */ +#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */ +#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */ + +/* Defines for sc_pad_wakeup_t */ +#define SC_PAD_WAKEUP_OFF 0U /* Off */ +#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */ +#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */ +#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */ +#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */ +#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */ + +#endif /* SC_PAD_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h new file mode 100644 index 0000000000..9008b85c6f --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_PM_API_H +#define SC_PM_API_H + +/* Defines for sc_pm_power_mode_t */ +#define SC_PM_PW_MODE_OFF 0U /* Power off */ +#define SC_PM_PW_MODE_STBY 1U /* Power in standby */ +#define SC_PM_PW_MODE_LP 2U /* Power in low-power */ +#define SC_PM_PW_MODE_ON 3U /* Power on */ + +/* Defines for sc_pm_clk_t */ +#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */ +#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */ +#define SC_PM_CLK_PER 2U /* Peripheral clock */ +#define SC_PM_CLK_PHY 3U /* Phy clock */ +#define SC_PM_CLK_MISC 4U /* Misc clock */ +#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */ +#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */ +#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */ +#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */ +#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */ +#define SC_PM_CLK_CPU 2U /* CPU clock */ +#define SC_PM_CLK_PLL 4U /* PLL */ +#define SC_PM_CLK_BYPASS 4U /* Bypass clock */ + +/* Defines for sc_pm_clk_mode_t */ +#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */ +#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */ +#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */ +#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */ + +typedef u8 sc_pm_power_mode_t; +typedef u8 sc_pm_clk_t; +typedef u8 sc_pm_clk_mode_t; +typedef u8 sc_pm_clk_parent_t; +typedef u32 sc_pm_clock_rate_t; + +#endif /* SC_PM_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h new file mode 100644 index 0000000000..ed303881e7 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_RM_API_H +#define SC_RM_API_H + +#include <asm/arch/sci/types.h> + +/* Defines for type widths */ +#define SC_RM_PARTITION_W 5U /* Width of sc_rm_pt_t */ +#define SC_RM_MEMREG_W 6U /* Width of sc_rm_mr_t */ +#define SC_RM_DID_W 4U /* Width of sc_rm_did_t */ +#define SC_RM_SID_W 6U /* Width of sc_rm_sid_t */ +#define SC_RM_SPA_W 2U /* Width of sc_rm_spa_t */ +#define SC_RM_PERM_W 3U /* Width of sc_rm_perm_t */ + +/* Defines for ALL parameters */ +#define SC_RM_PT_ALL ((sc_rm_pt_t)UINT8_MAX) /* All partitions */ +#define SC_RM_MR_ALL ((sc_rm_mr_t)UINT8_MAX) /* All memory regions */ + +/* Defines for sc_rm_spa_t */ +#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */ +#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */ +#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */ +#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */ + +/* Defines for sc_rm_perm_t */ +#define SC_RM_PERM_NONE 0U /* No access */ +#define SC_RM_PERM_SEC_R 1U /* Secure RO */ +#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */ +#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */ +#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */ +#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */ +#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */ +#define SC_RM_PERM_FULL 7U /* Full access */ + +/* Types */ + +/*! + * This type is used to declare a resource partition. + */ +typedef u8 sc_rm_pt_t; + +/*! + * This type is used to declare a memory region. + */ +typedef u8 sc_rm_mr_t; + +/*! + * This type is used to declare a resource domain ID used by the + * isolation HW. + */ +typedef u8 sc_rm_did_t; + +/*! + * This type is used to declare an SMMU StreamID. + */ +typedef u16 sc_rm_sid_t; + +/*! + * This type is a used to declare master transaction attributes. + */ +typedef u8 sc_rm_spa_t; + +typedef u8 sc_rm_perm_t; + +#endif /* SC_RM_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h new file mode 100644 index 0000000000..9eadc88592 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/types.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_TYPES_H +#define SC_TYPES_H + +/* Includes */ +#include <linux/types.h> + +/* Defines */ +/* + * This type is used to declare a handle for an IPC communication + * channel. Its meaning is specific to the IPC implementation. + */ +typedef u64 sc_ipc_t; + +/* Defines for common frequencies */ +#define SC_32KHZ 32768U /* 32KHz */ +#define SC_10MHZ 10000000U /* 10MHz */ +#define SC_20MHZ 20000000U /* 20MHz */ +#define SC_25MHZ 25000000U /* 25MHz */ +#define SC_27MHZ 27000000U /* 27MHz */ +#define SC_40MHZ 40000000U /* 40MHz */ +#define SC_45MHZ 45000000U /* 45MHz */ +#define SC_50MHZ 50000000U /* 50MHz */ +#define SC_60MHZ 60000000U /* 60MHz */ +#define SC_66MHZ 66666666U /* 66MHz */ +#define SC_74MHZ 74250000U /* 74.25MHz */ +#define SC_80MHZ 80000000U /* 80MHz */ +#define SC_83MHZ 83333333U /* 83MHz */ +#define SC_84MHZ 84375000U /* 84.37MHz */ +#define SC_100MHZ 100000000U /* 100MHz */ +#define SC_125MHZ 125000000U /* 125MHz */ +#define SC_133MHZ 133333333U /* 133MHz */ +#define SC_135MHZ 135000000U /* 135MHz */ +#define SC_150MHZ 150000000U /* 150MHz */ +#define SC_160MHZ 160000000U /* 160MHz */ +#define SC_166MHZ 166666666U /* 166MHz */ +#define SC_175MHZ 175000000U /* 175MHz */ +#define SC_180MHZ 180000000U /* 180MHz */ +#define SC_200MHZ 200000000U /* 200MHz */ +#define SC_250MHZ 250000000U /* 250MHz */ +#define SC_266MHZ 266666666U /* 266MHz */ +#define SC_300MHZ 300000000U /* 300MHz */ +#define SC_312MHZ 312500000U /* 312.5MHZ */ +#define SC_320MHZ 320000000U /* 320MHz */ +#define SC_325MHZ 325000000U /* 325MHz */ +#define SC_333MHZ 333333333U /* 333MHz */ +#define SC_350MHZ 350000000U /* 350MHz */ +#define SC_372MHZ 372000000U /* 372MHz */ +#define SC_375MHZ 375000000U /* 375MHz */ +#define SC_400MHZ 400000000U /* 400MHz */ +#define SC_500MHZ 500000000U /* 500MHz */ +#define SC_594MHZ 594000000U /* 594MHz */ +#define SC_625MHZ 625000000U /* 625MHz */ +#define SC_640MHZ 640000000U /* 640MHz */ +#define SC_650MHZ 650000000U /* 650MHz */ +#define SC_667MHZ 666666667U /* 667MHz */ +#define SC_675MHZ 675000000U /* 675MHz */ +#define SC_700MHZ 700000000U /* 700MHz */ +#define SC_720MHZ 720000000U /* 720MHz */ +#define SC_750MHZ 750000000U /* 750MHz */ +#define SC_800MHZ 800000000U /* 800MHz */ +#define SC_850MHZ 850000000U /* 850MHz */ +#define SC_900MHZ 900000000U /* 900MHz */ +#define SC_1000MHZ 1000000000U /* 1GHz */ +#define SC_1060MHZ 1060000000U /* 1.06GHz */ +#define SC_1188MHZ 1188000000U /* 1.188GHz */ +#define SC_1260MHZ 1260000000U /* 1.26GHz */ +#define SC_1280MHZ 1280000000U /* 1.28GHz */ +#define SC_1300MHZ 1300000000U /* 1.3GHz */ +#define SC_1400MHZ 1400000000U /* 1.4GHz */ +#define SC_1500MHZ 1500000000U /* 1.5GHz */ +#define SC_1600MHZ 1600000000U /* 1.6GHz */ +#define SC_1800MHZ 1800000000U /* 1.8GHz */ +#define SC_2000MHZ 2000000000U /* 2.0GHz */ +#define SC_2112MHZ 2112000000U /* 2.12GHz */ + +/* Defines for 24M related frequencies */ +#define SC_8MHZ 8000000U /* 8MHz */ +#define SC_12MHZ 12000000U /* 12MHz */ +#define SC_19MHZ 19800000U /* 19.8MHz */ +#define SC_24MHZ 24000000U /* 24MHz */ +#define SC_48MHZ 48000000U /* 48MHz */ +#define SC_120MHZ 120000000U /* 120MHz */ +#define SC_132MHZ 132000000U /* 132MHz */ +#define SC_144MHZ 144000000U /* 144MHz */ +#define SC_192MHZ 192000000U /* 192MHz */ +#define SC_211MHZ 211200000U /* 211.2MHz */ +#define SC_240MHZ 240000000U /* 240MHz */ +#define SC_264MHZ 264000000U /* 264MHz */ +#define SC_352MHZ 352000000U /* 352MHz */ +#define SC_360MHZ 360000000U /* 360MHz */ +#define SC_384MHZ 384000000U /* 384MHz */ +#define SC_396MHZ 396000000U /* 396MHz */ +#define SC_432MHZ 432000000U /* 432MHz */ +#define SC_480MHZ 480000000U /* 480MHz */ +#define SC_600MHZ 600000000U /* 600MHz */ +#define SC_744MHZ 744000000U /* 744MHz */ +#define SC_792MHZ 792000000U /* 792MHz */ +#define SC_864MHZ 864000000U /* 864MHz */ +#define SC_960MHZ 960000000U /* 960MHz */ +#define SC_1056MHZ 1056000000U /* 1056MHz */ +#define SC_1104MHZ 1104000000U /* 1104MHz */ +#define SC_1200MHZ 1200000000U /* 1.2GHz */ +#define SC_1464MHZ 1464000000U /* 1.464GHz */ +#define SC_2400MHZ 2400000000U /* 2.4GHz */ + +/* Defines for A/V related frequencies */ +#define SC_62MHZ 62937500U /* 62.9375MHz */ +#define SC_755MHZ 755250000U /* 755.25MHz */ + +/* Defines for type widths */ +#define SC_FADDR_W 36U /* Width of sc_faddr_t */ +#define SC_BOOL_W 1U /* Width of sc_bool_t */ +#define SC_ERR_W 4U /* Width of sc_err_t */ +#define SC_RSRC_W 10U /* Width of sc_rsrc_t */ +#define SC_CTRL_W 6U /* Width of sc_ctrl_t */ + +/* Defines for sc_bool_t */ +#define SC_FALSE ((sc_bool_t)0U) +#define SC_TRUE ((sc_bool_t)1U) + +/* Defines for sc_err_t */ +#define SC_ERR_NONE 0U /* Success */ +#define SC_ERR_VERSION 1U /* Incompatible API version */ +#define SC_ERR_CONFIG 2U /* Configuration error */ +#define SC_ERR_PARM 3U /* Bad parameter */ +#define SC_ERR_NOACCESS 4U /* Permission error (no access) */ +#define SC_ERR_LOCKED 5U /* Permission error (locked) */ +#define SC_ERR_UNAVAILABLE 6U /* Unavailable (out of resources) */ +#define SC_ERR_NOTFOUND 7U /* Not found */ +#define SC_ERR_NOPOWER 8U /* No power */ +#define SC_ERR_IPC 9U /* Generic IPC error */ +#define SC_ERR_BUSY 10U /* Resource is currently busy/active */ +#define SC_ERR_FAIL 11U /* General I/O failure */ +#define SC_ERR_LAST 12U + +/* Defines for sc_ctrl_t. */ +#define SC_C_TEMP 0U +#define SC_C_TEMP_HI 1U +#define SC_C_TEMP_LOW 2U +#define SC_C_PXL_LINK_MST1_ADDR 3U +#define SC_C_PXL_LINK_MST2_ADDR 4U +#define SC_C_PXL_LINK_MST_ENB 5U +#define SC_C_PXL_LINK_MST1_ENB 6U +#define SC_C_PXL_LINK_MST2_ENB 7U +#define SC_C_PXL_LINK_SLV1_ADDR 8U +#define SC_C_PXL_LINK_SLV2_ADDR 9U +#define SC_C_PXL_LINK_MST_VLD 10U +#define SC_C_PXL_LINK_MST1_VLD 11U +#define SC_C_PXL_LINK_MST2_VLD 12U +#define SC_C_SINGLE_MODE 13U +#define SC_C_ID 14U +#define SC_C_PXL_CLK_POLARITY 15U +#define SC_C_LINESTATE 16U +#define SC_C_PCIE_G_RST 17U +#define SC_C_PCIE_BUTTON_RST 18U +#define SC_C_PCIE_PERST 19U +#define SC_C_PHY_RESET 20U +#define SC_C_PXL_LINK_RATE_CORRECTION 21U +#define SC_C_PANIC 22U +#define SC_C_PRIORITY_GROUP 23U +#define SC_C_TXCLK 24U +#define SC_C_CLKDIV 25U +#define SC_C_DISABLE_50 26U +#define SC_C_DISABLE_125 27U +#define SC_C_SEL_125 28U +#define SC_C_MODE 29U +#define SC_C_SYNC_CTRL0 30U +#define SC_C_KACHUNK_CNT 31U +#define SC_C_KACHUNK_SEL 32U +#define SC_C_SYNC_CTRL1 33U +#define SC_C_DPI_RESET 34U +#define SC_C_MIPI_RESET 35U +#define SC_C_DUAL_MODE 36U +#define SC_C_VOLTAGE 37U +#define SC_C_PXL_LINK_SEL 38U +#define SC_C_OFS_SEL 39U +#define SC_C_OFS_AUDIO 40U +#define SC_C_OFS_PERIPH 41U +#define SC_C_OFS_IRQ 42U +#define SC_C_RST0 43U +#define SC_C_RST1 44U +#define SC_C_SEL0 45U +#define SC_C_LAST 46U + +#define SC_P_ALL ((sc_pad_t)UINT16_MAX) /* All pads */ + +/* Types */ + +/* This type is used to store a boolean */ +typedef u8 sc_bool_t; + +/* This type is used to store a system (full-size) address. */ +typedef u64 sc_faddr_t; + +/* This type is used to indicate error response for most functions. */ +typedef u8 sc_err_t; + +/* + * This type is used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +typedef u16 sc_rsrc_t; + +/* This type is used to indicate a control. */ +typedef u8 sc_ctrl_t; + +/* + * This type is used to indicate a pad. Valid values are SoC specific. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +typedef u16 sc_pad_t; + +#endif /* SC_TYPES_H */