Guys,
I think I have found a reason / partial fix, after getting some parameters tweaked and pimping out the debug routine to printf() almost the entire SPD table here is what I found.
1) The SPD tables for DDR1 and DDR2 are dfferent by about 10-15%. We'll need to add a separate SPD struct to fully make this elegant, for now I think enough of it is similar to gut shoot a quick fix. i.e. byte 23, 24, 25 etc have different meanings.
2) Some DIMMs are supporting 50-Ohm ODT termination, however some newer DIMMs have disabled this feature. The spd->dev_attr holds the actual value, 0x03 is with ODT 50Ohm and 0x01 is without. The 0x01 is for weak drivers.
Right now the code doesn't deal with anything on the dev_attr field. Turning on 2T timing seems to correct for this problem.
So the real question begins, what happens now?? Impedance can be worked around by excessively slowing the memory bus to compensate for the noise made by unmatched impedance. However, it would be nice to make this match, and actually use what we pay for. I know Freescale has some bits in the 83xx that deal with ODT and Impedance on the drivers. We'll need to add code to handle this, but more importantly I need to find what it means if the 50-Ohm ODT is not there in the DIMM, and how we compensate.
3) Lastly the cheap, but global fix to have the SPD code work for all newer memory types is to modify the picos_to_clks() function. I added a simple "#ifdef CFG_DDR2_LOOSE_TIMING" option that simply adds one extra clk++; This made all the PC4200 and PC5300 RAM I had work.
None of these is the 'correct' fix, but if somebody wants the code I'll be happy to post. I will be working with Freescale to find info on the ODT-50-ohm problem and possible other solutions.
-Russ
-----Original Message----- From: Bruce_Leonard@selinc.com [mailto:Bruce_Leonard@selinc.com] Sent: Tuesday, June 03, 2008 5:34 PM To: rmcguire@videopresence.com Cc: 'David Hawkins'; 'Steve Hensley'; u-boot-users@lists.sourceforge.net Subject: RE: [U-Boot-Users] 83xx SPD_EEPROM DDR2 Issues
"Russell McGuire" rmcguire@videopresence.com wrote on 06/03/2008 04:15:55 PM:
I haven't gone through the rest yet, but most likely if we want to keep
SPD
working for DDR2, we'll have to add the DDR2 definitions SPD into the
code,
as it looks like the DDR2 port is only partially complete.
-Russ
Russ,
That's pretty much jives with my recollection. One other thing that leaps to mind was the calculation for max_bus_clk. I hand cranked through that with a high clock rate as input and due to rounding errors got a bogus value. I don't remember the details right off the top of my head but it seems to me that the net result was I started with a bus clock that should have landed max_data_rate in one of those if-if-else-if cases, but it didn't. So I think that whole function (and especially the max_bus_clk calculation) needs to be gone through. Good luck. I'd help but I have my own issues with MTD :(.
Bruce