i.MX6UL defines speed grading in OCOTP register 0x440[17:16] as follows: 00 reserved 01 528MHz 10 700MHz 11 reserved
This commit removes the constants (which had the speed hardcoded in their names) and uses values instead.
Signed-off-by: Hector Palacios hector.palacios@digi.com --- arch/arm/cpu/armv7/mx6/soc.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index d4b22ad7f315..49b5773b1b77 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -103,10 +103,6 @@ u32 get_cpu_rev(void) * defines a 2-bit SPEED_GRADING */ #define OCOTP_CFG3_SPEED_SHIFT 16 -#define OCOTP_CFG3_SPEED_800MHZ 0 -#define OCOTP_CFG3_SPEED_850MHZ 1 -#define OCOTP_CFG3_SPEED_1GHZ 2 -#define OCOTP_CFG3_SPEED_1P2GHZ 3
u32 get_cpu_speed_grade_hz(void) { @@ -122,18 +118,23 @@ u32 get_cpu_speed_grade_hz(void)
switch (val) { /* Valid for IMX6DQ */ - case OCOTP_CFG3_SPEED_1P2GHZ: + case 3: if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) return 1200000000; - /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ - case OCOTP_CFG3_SPEED_1GHZ: - return 996000000; - /* Valid for IMX6DQ */ - case OCOTP_CFG3_SPEED_850MHZ: + /* Valid for IMX6SX/IMX6SDL/IMX6DQ/IMX6UL */ + case 2: + if (is_cpu_type(MXC_CPU_MX6UL)) + return 700000000; + else + return 996000000; + /* Valid for IMX6DQ/IMX6UL */ + case 1: if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) return 852000000; + else if (is_cpu_type(MXC_CPU_MX6UL)) + return 528000000; /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ - case OCOTP_CFG3_SPEED_800MHZ: + case 0: return 792000000; } return 0;