On 09/09/11 18:51, Flash K wrote:
Hi Graeme,
I was going through the U-boot code. Could you please help me with the following? I wanted to know as to where the CPU interrupts are initialised.
look in arch/x86/lib/board.c for init_sequence_f and init_sequence_r - These arrays show the init sequence for pre-relocated U-Boot and relocated U-Boot respectively.
Now interrupts are a bit tricky - interrupt_init() which is called directly in the post-relocation sequence actually initialises the programmable interrupt controller (PIC). CPU level interrupts (exceptions etc) are actually initialised in cpu_init_r() - For a stock x86 build, this is actually aliased to x86_cpu_init_r() which you will find in arch/x86/cpu/cpu.c
So the IDT (Interrupt Descriptor Table) is actually initialised immediately after relocation and then the PIC a little later on. Once the IDT is loaded, CPU exceptions can be handled and after the PIC is initialised, external interrupts (from devices) can be handled.
I believe it should be along with the CPU initialisation and before the
Yes, it is
northbridge and southbridge intialisation. I wanted to implement a logic to
Well, currently the x86 port has no concept of North and South bridges. For such a system, the Northbridge may contain the SDRAM controller and may need to be initialised (at least partially) first
read the state of a GPIO pin and carry out some action based on this key press. I want to do this before the Bootloader is invoked.
board_early_init_f and board_early_init_r are you best bets to put this kind of logic. board_early_init_f is extremely early - You may not have GPIO set up (unless it sets it up). board_early_init_r is called just after the CPU interrupts are enabled but before the PIC has been configured
Regards,
Graeme