Re: [U-Boot] [PATCH 2/3] LS102XA:workaround:disable priorities within DDR

On 08/13/2015 11:54 PM, Yuan Yao wrote:

EDDRTQCFG Registers are Integration Strap values which controls performance parameters for DDR Controller.

The bit 25 is used to disable priorities within DDR since DDR are connected backwards on silicon Rev2.0.

Signed-off-by: Yuan Yao yao.yuan@freescale.com

board/freescale/ls1021aqds/ls1021aqds.c | 13 ++++++++++++- board/freescale/ls1021atwr/ls1021atwr.c | 13 ++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-)

Yuan,

SoC erratum workaround shouldn't be put into board file.

York