Apollo Lake is an Intel SoC generation aimed at relatively low-end embedded systems. It was released in 2016 but has become more popular recently with some embedded boards using it.
This series adds support for Apollo Lake. As an example it adds an implementation of chromebook_coral (a large range of Chromebooks released in 2017).
The series provides enough support to boot to a prompt. with LCD display, storage, USB, EC and keyboard.
Since this is the first time U-Boot has used FSP2 there is quite a bit of refactoring needed.
This series is available at u-boot-dm/coral-working
Changes in v7: - Add a comment to enable_bios_reset_cpl() - Add the new documentation to the index file - Drop Glacier Lake code - Fix value of GPIO_28_IRQ - Update Kconfig to avoid using def_bool - Update comment in apl_p2sb_early_init()
Changes in v6: - Add .driver_data in the designware_pci_supported array - Add a comment about VANILLA - Add a comment about the need for board_run_command() - Add new patch with methods to find the position/size of next SPL phase - Change comment to apl_hostbridge_early_init_pinctrl, not apl_gpio_early_init - Change commented-out enable_rtc_upper_bank() call to a TODO - Drop Glacier Lake code - Drop init of ComB since it is not used - Drop lpc_configure_pads() and probe() function, add a comment about pads - Drop mention of devicetree for VTD feature - Drop mention of ramstage - Drop platform data and pre-PCI code, since DM PCI is available in SPL - Drop unnecessary priv struct and probe method - Fix FSP-M and FSP-S in comments - Fix comments for struct apl_hostbridge_platdata - Fix various coding style problems - Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option - Move image pos/size access functions and symbols to generic SPL code - Move lpss_reset_release() to this commit - Rename init_for_uart() to board_debug_uart_init() - Use 'No SPI' instead of 'SPI2' as a debug message - Use SZ_4G instead of open-coded shift - Use generic gpio compatible string
Changes in v5: - Add L2 cache flush function - Add L2 cache flush functoin - Add gpio-controller to GPIO nodes - Allocate the FSP-S data instead of using the stack - Comment out GPIOs in the fsp_s node since we don't use them yet - Correct CPU ACPI IDs - Drop SAFETY_MARGIN - Drop unrelated change metioned by Heiko - Enable SMP - Rename APOLLOLAKE_USB2_PORT_MAX - Use a define for ACPI base address
Changes in v4: - Add a comment for enable_bios_reset_cpl() - Add comments for exported functions - Add u-boot,skip-auto-config-until-reloc property to PCI - Adjust the comment for struct dw_i2c_speed_config - Allow pinctrl nodes to have subnodes (i.e. GPIO nodes) - Avoid needing to know internals of pinctrl in this driver - Change apollolake to apl - Detect zero mmio address - Drop GPIO_NUM_PAD_CFG_REGS - Drop duplicate commit 'Create a new sandbox_pci_read_bar() function' - Enable HAVE_X86_FIT - Enable INTEL_GPIO - Move code to pinctrl driver - Name this P-Unit instead of power unit, in the commit message - New GPIO driver binding - Rename arch_fsp_s_preinit() to arch_fsps_preinit() - Set up LPC pads early - Switch over to use pinctrl for pad init/config - Tidy up header guards - Tidy up mixed case in FSP code - Tidy up the header file a little - Update SPI flash protection only in SPL - Update documentation with more detailed memory map - Use 'Apollo Lake' - Use BIT() macro a bit more - Use BIT() macro bit more - Use existing VBT Kconfig option - Use hyphen for device-tree properties - Use tabs instead of spaces - apollolake -> Apollo Lake - use GENMASK() for VTBAR_MASK
Changes in v3: - Ad FSP-S support - Add CONFIG_TPL_X86_ASSUME_CPUID to reduce code size - Add Chrome OS EC support - Add MMC, video, USB configs - Add VBT signature - Add a driver for APL SPI for TPL (using of-platdata) - Add a proper SPI node and make the SPI flash node a child - Add a weak function to avoid errors on other platforms - Add an APL_SPI_FLASH_BOOT option to enable non-mmap boot - Add bootstage support - Add bootstage timing for reading vbt - Add fspm_done() hook to handle FSP-S wierdness (it breaks SPI flash) - Add more documentation - Add snapshot/restore for IRQs - Add spi alias in device tree - Add structures for FSP-S also - Add two more defines for the CPU driver - Add various minor tidy-ups - Adjust fast_spi_cache_bios_region() to avoid using SPI driver - Disable the bootcommand since it does nothing useful on coral - Don't allow BOOT_FROM_FAST_SPI_FLASH with FSP-S - Don't enable SPI flash in TPL by default - Drop CONFIG_SPL_NET_SUPPORT - Drop calls to x86_cpu_init_f(), x86_cpu_reinit_f() - Drop patch '86: timer: Reduce timer code size in TPL on Intel CPUs' - Drop patch 'dm: core: Don't include ofnode functions with of-platdata' - Drop patch 'spi: sandbox: Add a test driver for sandbox SPI flash' - Drop patch 'spl: Allow SPL/TPL to use of-platdata without libfdt' - Drop patch 'x86: apollolake: Add definitions for the Intel Fast SPI interface' - Drop patch 'x86: timer: Set up the timer in timer_early_get_count()' - Drop struct fsp_usp_header as it is now in the API file - Drop unused code in lpc_configure_pads() - Enable video and USB3 - Expand comments for BOOT_FROM_FAST_SPI_FLASH - Fix build error when debug UART is disabled - Fix mixed case in GPIO defines - Fix the incorrect value of CPU_ADDR_BITS - Fix value of LPC_BC_LE - Init the p2sb before the northbridge since the latter so it can use GPIOs - Move location of fast_spi.h header file - Move pad programming into the hostbridge to reduce TPL device-tree size - Reduce amount of early-pad data in TPL - Rework how pads configuration is defined in TPL and SPL - Set boot_loader_tolum_size to 0 - Shorten log_msg_ret() calls since the function name is always printed - Support TPL without CONFIG_TPL_SPI_SUPPORT - Support TPL without CONFIG_TPL_SPI_SUPPORT (reduces code size) - Support bootstage timing - Tidy up the pad settings in the device tree - Use a zero-based tsc timer - Use pci_get_devfn() - Use the IRQ uclass instead of ITSS
Changes in v2: - Drop probe() function - Implement set_spi_protect()
Simon Glass (17): x86: apl: Add pinctrl driver i2c: designware: Add Apollo Lake support x86: apl: Add systemagent driver x86: apl: Add hostbridge driver x86: apl: Add ITSS driver x86: apl: Add LPC driver x86: apl: Add PCH driver x86: apl: Add PUNIT driver spl: Add methods to find the position/size of next phase x86: apl: Add SPL loaders x86: apl: Add a CPU driver x86: apl: Add SPL/TPL init x86: apl: Add P2SB driver x86: apl: Add Kconfig and Makefile x86: apl: Add FSP structures x86: apl: Add FSP support x86: Add chromebook_coral
arch/x86/Kconfig | 1 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/apollolake/Kconfig | 96 ++ arch/x86/cpu/apollolake/Makefile | 21 + arch/x86/cpu/apollolake/cpu.c | 41 + arch/x86/cpu/apollolake/cpu_common.c | 17 + arch/x86/cpu/apollolake/cpu_spl.c | 271 ++++++ arch/x86/cpu/apollolake/fsp_m.c | 210 +++++ arch/x86/cpu/apollolake/fsp_s.c | 661 ++++++++++++++ arch/x86/cpu/apollolake/hostbridge.c | 179 ++++ arch/x86/cpu/apollolake/itss.c | 214 +++++ arch/x86/cpu/apollolake/lpc.c | 122 +++ arch/x86/cpu/apollolake/p2sb.c | 166 ++++ arch/x86/cpu/apollolake/pch.c | 36 + arch/x86/cpu/apollolake/punit.c | 94 ++ arch/x86/cpu/apollolake/spl.c | 178 ++++ arch/x86/cpu/apollolake/systemagent.c | 23 + arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_coral.dts | 831 ++++++++++++++++++ arch/x86/include/asm/arch-apollolake/cpu.h | 20 + .../asm/arch-apollolake/fsp/fsp_configs.h | 14 + .../asm/arch-apollolake/fsp/fsp_m_upd.h | 123 +++ .../asm/arch-apollolake/fsp/fsp_s_upd.h | 292 ++++++ .../include/asm/arch-apollolake/fsp/fsp_vpd.h | 11 + arch/x86/include/asm/arch-apollolake/gpio.h | 485 ++++++++++ arch/x86/include/asm/arch-apollolake/itss.h | 43 + arch/x86/include/asm/arch-apollolake/lpc.h | 82 ++ arch/x86/include/asm/arch-apollolake/pch.h | 9 + .../include/asm/arch-apollolake/systemagent.h | 37 + arch/x86/include/asm/msr-index.h | 1 + board/google/Kconfig | 15 + board/google/chromebook_coral/Kconfig | 43 + board/google/chromebook_coral/MAINTAINERS | 6 + board/google/chromebook_coral/Makefile | 5 + board/google/chromebook_coral/coral.c | 19 + common/spl/spl.c | 20 + configs/chromebook_coral_defconfig | 102 +++ doc/board/google/chromebook_coral.rst | 241 +++++ doc/board/google/index.rst | 1 + drivers/i2c/designware_i2c_pci.c | 25 + drivers/pinctrl/intel/Kconfig | 16 +- drivers/pinctrl/intel/Makefile | 1 + drivers/pinctrl/intel/pinctrl_apl.c | 192 ++++ include/configs/chromebook_coral.h | 32 + include/spl.h | 21 +- 45 files changed, 5015 insertions(+), 4 deletions(-) create mode 100644 arch/x86/cpu/apollolake/Kconfig create mode 100644 arch/x86/cpu/apollolake/cpu.c create mode 100644 arch/x86/cpu/apollolake/cpu_common.c create mode 100644 arch/x86/cpu/apollolake/cpu_spl.c create mode 100644 arch/x86/cpu/apollolake/fsp_m.c create mode 100644 arch/x86/cpu/apollolake/fsp_s.c create mode 100644 arch/x86/cpu/apollolake/hostbridge.c create mode 100644 arch/x86/cpu/apollolake/itss.c create mode 100644 arch/x86/cpu/apollolake/lpc.c create mode 100644 arch/x86/cpu/apollolake/p2sb.c create mode 100644 arch/x86/cpu/apollolake/pch.c create mode 100644 arch/x86/cpu/apollolake/punit.c create mode 100644 arch/x86/cpu/apollolake/spl.c create mode 100644 arch/x86/cpu/apollolake/systemagent.c create mode 100644 arch/x86/dts/chromebook_coral.dts create mode 100644 arch/x86/include/asm/arch-apollolake/cpu.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h create mode 100644 arch/x86/include/asm/arch-apollolake/gpio.h create mode 100644 arch/x86/include/asm/arch-apollolake/itss.h create mode 100644 arch/x86/include/asm/arch-apollolake/lpc.h create mode 100644 arch/x86/include/asm/arch-apollolake/pch.h create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h create mode 100644 board/google/chromebook_coral/Kconfig create mode 100644 board/google/chromebook_coral/MAINTAINERS create mode 100644 board/google/chromebook_coral/Makefile create mode 100644 board/google/chromebook_coral/coral.c create mode 100644 configs/chromebook_coral_defconfig create mode 100644 doc/board/google/chromebook_coral.rst create mode 100644 drivers/pinctrl/intel/pinctrl_apl.c create mode 100644 include/configs/chromebook_coral.h