Added onenand_ipl/board/poseidon directory and onenand IPL specific files for poseidon in it.
Signed-off-by: Vivek Dalal v.dalal@samsung.com --- onenand_ipl/board/poseidon/Makefile | 84 +++++++++++++++++++++++++ onenand_ipl/board/poseidon/config.mk | 14 ++++ onenand_ipl/board/poseidon/low_levelinit.S | 173 +++++++++++++++++++++++++++++++++++++++++++++++++++++ onenand_ipl/board/poseidon/poseidon.c | 70 +++++++++++++++++++++ onenand_ipl/board/poseidon/u-boot.onenand.lds | 53 ++++++++++++++++ 5 files changed, 394 insertions(+)
diff --git a/onenand_ipl/board/poseidon/Makefile b/onenand_ipl/board/poseidon/Makefile index e69de29..6d3ec9d 100644 --- a/onenand_ipl/board/poseidon/Makefile +++ b/onenand_ipl/board/poseidon/Makefile @@ -0,0 +1,84 @@ + +include $(TOPDIR)/config.mk +include $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_ONENAND_IPL +CFLAGS += -DCONFIG_ONENAND_IPL +OBJCLFAGS += --gap-fill=0x00 + +SOBJS := low_levelinit.o +SOBJS += start.o +COBJS := poseidon.o +COBJS += onenand_read.o +COBJS += onenand_boot.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR) + +onenandobj := $(OBJTREE)/onenand_ipl/ + +ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin $(onenandobj)onenand-ipl-4k.bin + +all: $(obj).depend $(ALL) + +$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x800 -O binary $< $@ + +$(onenandobj)onenand-ipl-4k.bin: $(onenandobj)onenand-ipl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x1000 -O binary $< $@ + +$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(onenandobj)onenand-ipl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + -Map $@.map -o $@ + +# create symbolic links from common files + +# from cpu directory +$(obj)start.S: + @rm -f $@ + ln -s $(SRCTREE)/cpu/$(CPU)/start.S $@ + +# from onenand_ipl directory +$(obj)onenand_ipl.h: + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $@ + +$(obj)onenand_boot.c: $(obj)onenand_ipl.h + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $@ + +$(obj)onenand_read.c: $(obj)onenand_ipl.h + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $@ + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)poseidon.c: + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/poseidon.c $@ + +$(obj)low_levelinit.S: + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/low_levelinit.S $@ +endif + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)$.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/onenand_ipl/board/poseidon/config.mk b/onenand_ipl/board/poseidon/config.mk index e69de29..1f95da1 100644 --- a/onenand_ipl/board/poseidon/config.mk +++ b/onenand_ipl/board/poseidon/config.mk @@ -0,0 +1,12 @@ +# +# (C) Copyright 2009-2010 Samsung Electronics +# Vivek Dalal v.dalal@samsung.com +# +# Samsung Poseidon board with OMAP2430 (ARM1136) cpu +# +# Physical Address: +# 8000'0000 (bank0) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +TEXT_BASE = 0x00000000 diff --git a/onenand_ipl/board/poseidon/low_levelinit.S b/onenand_ipl/board/poseidon/low_levelinit.S index e69de29..057b710 100644 --- a/onenand_ipl/board/poseidon/low_levelinit.S +++ b/onenand_ipl/board/poseidon/low_levelinit.S @@ -0,0 +1,173 @@ +/* + * Board specific setup info + * + * (C) Copyright 2009-2010 Samsung Electronics + * Vivek Dalal v.dalal@samsung.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/omap24xx.h> +#include <asm/arch/mem.h> +#include <asm/arch/clocks.h> + + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +.globl lowlevel_init +lowlevel_init: + mov r3, r0 /* save skip information */ + + +@; Disable watch dog + ldr r0, =WD2_BASE @; 0x49016000 + ldr r1, =0xaaaa + str r1, [r0, #0x48] @; WD2_WSPR 0x49016048 + + mov r1, r1, lsr #1 + str r1, [r0, #0x48] @; WD2_WSPR 0x49016048 + +@;Configure the Core clock source to be DPLL, by default it is DPLL * 2 + ldr r0, = 0x49006000 +loop3: + mov r1, #0x00000083 + str r1, [r0, #0x60] @; PRCM_CLKSRC_CTRL 0x49006060 + +@; at reset Low bypass mode set, so no need to reset + mov r1, #0x00000002 + str r1, [r0, #0x140]@; CM_CLKSEL_MPU 0x49006140 + + ldr r1, =0x08501044 + str r1, [r0, #0x240]@; CM_CLKSEL1_CORE 0x49006240 + ldr r1, =0x0114AC00 + str r1, [r0, #0x540]@; CM_CLKSEL1_PLL 0x49006540 + +loop5: + ldr r1, [r0, #0x84] @; PRCM_CLKCFG_STATUS 0x49006084 + cmp r1, #0x00 + bne loop5 + + mov r1, #0x01 + str r1, [r0, #0x80] @; PRCM_CLKCFG_CTRL 0x49006080 + +loop6: + ldr r1, [r0, #0x80] @; PRCM_CLKCFG_CTRL 0x49006080 + cmp r1, #0x00 + bne loop6 + + mov r1, #0x0000000F + str r1, [r0, #0x500] @; CM_CLKEN_PLL 0x49006500 + nop + nop + nop + +loop7: + ldr r1, [r0, #0x520]@; CM_IDLEST_CKGEN 0x49006520 + and r1, r1, #0x03 + cmp r1, #0x02 + bne loop7 + nop + nop +@; SDRC setting + mov r0, #0x6D000000 + mov r1, #0x00000012 + str r1, [r0, #0x10] @; SDRC_SYSCONFIG 0x6D000010 + nop + nop + nop + mov r1, #0x5000 @; wait 200us +loop10: + subs r1, r1, #0x01 + bne loop10 + + mov r1, #0x00000010 + str r1, [r0, #0x10] @; SDRC_SYSCONFIG 0x6D000010 + + mov r1, #0x100 + str r1, [r0, #0x44] @; SDRC_SHARING 0x6D000044 + + + ldr r1, =0x01A02011 + str r1, [r0, #0x80] @; SDRC_MCFG_0 0x6D000080 + + ldr r1, =0x629DB4C6 + str r1, [r0, #0x9C] @; SDRC_ACTIM_CTRLA_0 0x6D00009C + + ldr r1, =0x00002014 + str r1, [r0, #0xA0] @; SDRC_ACTIM_CTRLB_0 0x6D0000A0 + + ldr r1, =0x0004E201 + str r1, [r0, #0xA4] @; SDRC_RFR_CTRL_0 0x6D0000A4 + + mov r1, #0x00000000 + str r1, [r0, #0xA8] @; SDRC_MANUAL_0 0x6D0000A8 + + mov r1, #0x00000001 + str r1, [r0, #0xA8] @; SDRC_MANUAL_0 0x6D0000A8 + + mov r1, #0x00000002 + str r1, [r0, #0xA8] @; SDRC_MANUAL_0 0x6D0000A8 + + mov r1, #0x00000002 + str r1, [r0, #0xA8] @; SDRC_MANUAL_0 0x6D0000A8 + + mov r1, #0x00000032 + str r1, [r0, #0x84] @; SDRC_MR_0 0x6D000084 + + ldr r1, =0x0000170C + str r1, [r0, #0x60] @; SDRC_DLLA_CTRL 0x6D000060 + + sub r2, r1, #0x4 @; r2 = 0x00001708 + str r2, [r0, #0x60] @; SDRC_DLLA_CTRL 0x6D000060 + + ldr r1, =0x0000170C + str r1, [r0, #0x68] @; SDRC_DLLB_CTRL 0x6D000068 + + sub r2, r1, #0x4 @; r2 = 0x00001708 + str r2, [r0, #0x68] @; SDRC_DLLB_CTRL 0x6D000068 + + nop + nop + nop + +@;Wait until dram is stable + mov r2, #0x1800 +1: + subs r2, r2, #0x1 + bne 1b + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + mov r0, r3 /* pass skip info to s_init */ + + bl s_init /* go setup pll,mux,memory */ + + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK diff --git a/onenand_ipl/board/poseidon/poseidon.c b/onenand_ipl/board/poseidon/poseidon.c index e69de29..bb2b6e9 100644 --- a/onenand_ipl/board/poseidon/poseidon.c +++ b/onenand_ipl/board/poseidon/poseidon.c @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2009-2010 Samsung Electronics + * Vivek Dalal v.dalal@samsung.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/arch/mux.h> +#include <asm/io.h> + +#define write_config_reg(reg, value) writeb(value, reg) + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + return 0; +} + +#ifdef CONFIG_SYS_PRINTF +/* Pin Muxing registers used for UART1 */ +/**************************************** + * Routine: muxSetupUART1 (ostboot) + * Description: Set up uart1 muxing + *****************************************/ + +void muxSetupUART1(void) +{ + /* UART1_CTS pin configuration, PIN = D21 */ + write_config_reg(CONTROL_PADCONF_UART1_CTS, 0); + /* UART1_RTS pin configuration, PIN = H21 */ + write_config_reg(CONTROL_PADCONF_UART1_RTS, 0); + /* UART1_TX pin configuration, PIN = L20 */ + write_config_reg(CONTROL_PADCONF_UART1_TX, 0); + /* UART1_RX pin configuration, PIN = T21 */ + write_config_reg(CONTROL_PADCONF_UART1_RX, 0); +} + +#endif + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called at time when only stack is available. + **********************************************************/ +int s_init(int skip) +{ +#ifdef CONFIG_SYS_PRINTF + muxSetupUART1(); +#endif + return 0; +} diff --git a/onenand_ipl/board/poseidon/u-boot.onenand.lds b/onenand_ipl/board/poseidon/u-boot.onenand.lds index e69de29..c2a8109 100644 --- a/onenand_ipl/board/poseidon/u-boot.onenand.lds +++ b/onenand_ipl/board/poseidon/u-boot.onenand.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2009-2010 Samsung Electronics + * Vivek Dalal v.dalal@samsung.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) . = ALIGN(4); } + _end = .; +}