Signed-off-by: Jens Gehrlein sew_s@tqs.de ---
board/tqc/tqma31/tqma31.c | 6 ++++++ include/asm-arm/arch-mx31/mx31-regs.h | 1 + include/configs/TQMA31.h | 7 +++++-- 3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/board/tqc/tqma31/tqma31.c b/board/tqc/tqma31/tqma31.c index dd2bb0a..30584fe 100644 --- a/board/tqc/tqma31/tqma31.c +++ b/board/tqc/tqma31/tqma31.c @@ -36,6 +36,12 @@ static void setup_chipselects (void) __REG (CSCR_L(0)) = CSCR_L_OEA_10 | CSCR_L_EBWA_3 | CSCR_L_EBWN_3 \ | CSCR_L_EBC_ONLY_WA | CSCR_L_DSZ_16_MUM0 | CSCR_L_CSEN;
+ /* FPGA configuration flash on CS1 */ + __REG (CSCR_U(1)) = CSCR_U_CNC_3 | CSCR_U_WSC_13 | CSCR_U_EDC_4; + __REG (CSCR_A(1)) = CSCR_A_RWA_2 | CSCR_A_RWN_2 | CSCR_A_LBN_2_MUM0; + __REG (CSCR_L(1)) = CSCR_L_OEA_10 | CSCR_L_EBWA_3 | CSCR_L_EBWN_3 \ + | CSCR_L_EBC_ONLY_WA | CSCR_L_DSZ_16_MUM0 | CSCR_L_CSEN; + /* Ethernet controller on CS4 */ __REG (CSCR_U(4)) = CSCR_U_CNC_1 | CSCR_U_WSC_22 | CSCR_U_EDC_4; __REG (CSCR_A(4)) = CSCR_A_RWA_2 | CSCR_A_RWN_15; diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index 407b2c6..69d7614 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -84,6 +84,7 @@ #define CSCR_U_WSC_9 0x00000900 #define CSCR_U_WSC_12 0x00000C00 #define CSCR_U_WSC_22 0x00001600 +#define CSCR_U_WSC_13 0x00000D00 #define CSCR_U_EDC_4 0x00000004 #define CSCR_U_EDC_13 0x0000000D
diff --git a/include/configs/TQMA31.h b/include/configs/TQMA31.h index a174940..504cb57 100644 --- a/include/configs/TQMA31.h +++ b/include/configs/TQMA31.h @@ -89,18 +89,21 @@ #define CFG_FLASH_BASE CS0_BASE
/* Max number of memory banks */ -#define CFG_MAX_FLASH_BANKS 4 +#define CFG_MAX_FLASH_BANKS 5
/* * Bank start addresses. * 4 x 32 MiB is the maximum for user and U-Boot code. Please adapt the list * as well as CFG_MAX_FLASH_BANKS to your TQM. Also consider dual die chips * or single die chips, e.g. one dual die chip represents two banks. + * The fifth bank is a separate chip for the FPGA configuration. It's + * controlled by chipselect 1. */ #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, \ CFG_FLASH_BASE + 32*1024*1024, \ CFG_FLASH_BASE + 64*1024*1024, \ - CFG_FLASH_BASE + 96*1024*1024} + CFG_FLASH_BASE + 96*1024*1024, \ + CS1_BASE}
/* Max number of sectors on one chip */ #define CFG_MAX_FLASH_SECT 259