Re: [PATCH v3 3/4] board: sifive: use ccache driver instead of helper function

On 8/17/21 5:08 AM, Zong Li wrote:

Invokes the common cache_init function to initialize ccache.

Signed-off-by: Zong Li zong.li@sifive.com

arch/riscv/cpu/fu540/Kconfig | 2 + arch/riscv/cpu/fu540/Makefile | 1 - arch/riscv/cpu/fu540/cache.c | 55 ----------------------- arch/riscv/cpu/fu740/Kconfig | 2 + arch/riscv/cpu/fu740/Makefile | 1 - arch/riscv/cpu/fu740/cache.c | 55 ----------------------- arch/riscv/include/asm/arch-fu540/cache.h | 14 ------ arch/riscv/include/asm/arch-fu740/cache.h | 14 ------ board/sifive/unleashed/unleashed.c | 12 +---- board/sifive/unmatched/unmatched.c | 11 +---- 10 files changed, 8 insertions(+), 159 deletions(-) delete mode 100644 arch/riscv/cpu/fu540/cache.c delete mode 100644 arch/riscv/cpu/fu740/cache.c delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h

diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index 05463b2625..1604b412b4 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -19,6 +19,8 @@ config SIFIVE_FU540 imply SMP imply CLK_SIFIVE imply CLK_SIFIVE_PRCI

• imply SIFIVE_CACHE
• imply SIFIVE_CCACHE imply SIFIVE_SERIAL imply MACB imply MII

diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile index 088205ef57..043fb961a5 100644 --- a/arch/riscv/cpu/fu540/Makefile +++ b/arch/riscv/cpu/fu540/Makefile @@ -8,5 +8,4 @@ obj-y += spl.o else obj-y += dram.o obj-y += cpu.o -obj-y += cache.o endif diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c deleted file mode 100644 index 0fc4ef6c00..0000000000 --- a/arch/riscv/cpu/fu540/cache.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Copyright (C) 2020 SiFive, Inc
• • Authors:
• • Pragnesh Patel pragnesh.patel@sifive.com
• */

-#include <common.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <linux/bitops.h>

-/* Register offsets */ -#define L2_CACHE_CONFIG 0x000 -#define L2_CACHE_ENABLE 0x008

-#define MASK_NUM_WAYS GENMASK(15, 8) -#define NUM_WAYS_SHIFT 8

-DECLARE_GLOBAL_DATA_PTR;

-int cache_enable_ways(void) -{

• const void *blob = gd->fdt_blob;
• int node;
• fdt_addr_t base;
• u32 config;
• u32 ways;
• volatile u32 *enable;
• node = fdt_node_offset_by_compatible(blob, -1,

• 			     "sifive,fu540-c000-ccache");
  

• if (node < 0)

• return node;
  

• base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,

• 				NULL, false);
  

• if (base == FDT_ADDR_T_NONE)

• return FDT_ADDR_T_NONE;
  

• config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
• ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
• enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
• /* memory barrier */
• mb();
• (*enable) = ways - 1;
• /* memory barrier */
• mb();
• return 0;

-} diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig index 408195f149..049a0a0584 100644 --- a/arch/riscv/cpu/fu740/Kconfig +++ b/arch/riscv/cpu/fu740/Kconfig @@ -19,6 +19,8 @@ config SIFIVE_FU740 imply SMP imply CLK_SIFIVE imply CLK_SIFIVE_PRCI

• imply SIFIVE_CACHE
• imply SIFIVE_CCACHE imply SIFIVE_SERIAL imply MACB imply MII

diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile index 5ef8ac18a7..1d1ad98ba7 100644 --- a/arch/riscv/cpu/fu740/Makefile +++ b/arch/riscv/cpu/fu740/Makefile @@ -8,5 +8,4 @@ obj-y += spl.o else obj-y += dram.o obj-y += cpu.o -obj-y += cache.o endif diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c deleted file mode 100644 index 680955c9e3..0000000000 --- a/arch/riscv/cpu/fu740/cache.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Copyright (C) 2020-2021 SiFive, Inc
• • Authors:
• • Pragnesh Patel pragnesh.patel@sifive.com
• */

-#include <common.h> -#include <asm/io.h> -#include <linux/bitops.h> -#include <asm/global_data.h>

-/* Register offsets */ -#define L2_CACHE_CONFIG 0x000 -#define L2_CACHE_ENABLE 0x008

-#define MASK_NUM_WAYS GENMASK(15, 8) -#define NUM_WAYS_SHIFT 8

-DECLARE_GLOBAL_DATA_PTR;

-int cache_enable_ways(void) -{

• const void *blob = gd->fdt_blob;
• int node;
• fdt_addr_t base;
• u32 config;
• u32 ways;
• volatile u32 *enable;
• node = fdt_node_offset_by_compatible(blob, -1,

• 			     "sifive,fu740-c000-ccache");
  

• if (node < 0)

• return node;
  

• base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,

• 				NULL, false);
  

• if (base == FDT_ADDR_T_NONE)

• return FDT_ADDR_T_NONE;
  

• config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
• ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
• enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
• /* memory barrier */
• mb();
• (*enable) = ways - 1;
• /* memory barrier */
• mb();
• return 0;

-} diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h deleted file mode 100644 index 135a17c679..0000000000 --- a/arch/riscv/include/asm/arch-fu540/cache.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Copyright (C) 2020 SiFive, Inc.
• • Authors:
• • Pragnesh Patel pragnesh.patel@sifve.com
• */

-#ifndef _CACHE_SIFIVE_H -#define _CACHE_SIFIVE_H

-int cache_enable_ways(void);

-#endif /* _CACHE_SIFIVE_H */ diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h deleted file mode 100644 index 7d4fe9942b..0000000000 --- a/arch/riscv/include/asm/arch-fu740/cache.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Copyright (C) 2020-2021 SiFive, Inc.
• • Authors:
• • Pragnesh Patel pragnesh.patel@sifve.com
• */

-#ifndef _CACHE_SIFIVE_H -#define _CACHE_SIFIVE_H

-int cache_enable_ways(void);

-#endif /* _CACHE_SIFIVE_H */ diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c index 43027f0b54..6d697d797d 100644 --- a/board/sifive/unleashed/unleashed.c +++ b/board/sifive/unleashed/unleashed.c @@ -15,7 +15,7 @@ #include <linux/delay.h> #include <misc.h> #include <spl.h> -#include <asm/arch/cache.h> +#include <asm/cache.h> #include <asm/sections.h>

/* @@ -126,14 +126,6 @@ void *board_fdt_blob_setup(void)

int board_init(void) {

• int ret;
• /* enable all cache ways */
• ret = cache_enable_ways();
• if (ret) {

• debug("%s: could not enable cache ways\n", __func__);
  

• return ret;
  

• }
• return 0;

• return cache_init(); }

diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c index 2f5629b578..f4fc2a793d 100644 --- a/board/sifive/unmatched/unmatched.c +++ b/board/sifive/unmatched/unmatched.c @@ -8,7 +8,7 @@

#include <common.h> #include <dm.h> -#include <asm/arch/cache.h> +#include <asm/cache.h> #include <asm/sections.h>

#if defined(CONFIG_OF_SEPARATE) @@ -23,13 +23,6 @@ void *board_fdt_blob_setup(void)

int board_init(void) {

• int ret;
• /* enable all cache ways */
• ret = cache_enable_ways();
• if (ret) {

• debug("%s: could not enable cache ways\n", __func__);
  

• return ret;
  

• }
• return 0;

• return cache_init(); }

Reviewed-by: Sean Anderson seanga2@gmail.com