PRCM, timer base addresses and offsets are different from AM33xx. Updating the same.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- Changes since V2: -> Dropped updating wrong address for TI81XX
arch/arm/include/asm/arch-am33xx/cpu.h | 17 +++++++++++------ arch/arm/include/asm/arch-am33xx/hardware.h | 7 ------- arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 2 ++ arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 2 ++ 4 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 05752ce..19b8469 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -237,6 +237,14 @@ struct cm_perpll { unsigned int cpswclkstctrl; /* offset 0x144 */ unsigned int lcdcclkstctrl; /* offset 0x148 */ }; + +/* Encapsulating Display pll registers */ +struct cm_dpll { + unsigned int resv1[2]; + unsigned int clktimer2clk; /* offset 0x08 */ + unsigned int resv2[10]; + unsigned int clklcdcpixelclk; /* offset 0x34 */ +}; #else /* Encapsulating core pll registers */ struct cm_wkuppll { @@ -392,15 +400,12 @@ struct cm_perpll { unsigned int resv40[7]; unsigned int cpgmac0clkctrl; /* offset 0xB20 */ }; -#endif /* CONFIG_AM43XX */
-/* Encapsulating Display pll registers */ struct cm_dpll { - unsigned int resv1[2]; - unsigned int clktimer2clk; /* offset 0x08 */ - unsigned int resv2[10]; - unsigned int clklcdcpixelclk; /* offset 0x34 */ + unsigned int resv1; + unsigned int clktimer2clk; /* offset 0x04 */ }; +#endif /* CONFIG_AM43XX */
/* Control Module RTC registers */ struct cm_rtc { diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index ee5fce0..dd950e5 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -48,13 +48,6 @@ #define EMIF4_0_CFG_BASE 0x4C000000 #define EMIF4_1_CFG_BASE 0x4D000000
-/* PLL related registers */ -#define CM_DPLL 0x44E00500 -#define CM_DEVICE 0x44E00700 -#define CM_RTC 0x44E00800 -#define CM_CEFUSE 0x44E00A00 -#define PRM_DEVICE 0x44E00F00 - /* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index e4231c8..c67a080 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -30,6 +30,8 @@ #define PRCM_BASE 0x44E00000 #define CM_PER 0x44E00000 #define CM_WKUP 0x44E00400 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800
#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) #define PRM_RSTST (PRM_RSTCTRL + 8) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 3b665e6..8fee929 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -30,6 +30,8 @@ #define PRCM_BASE 0x44DF0000 #define CM_WKUP 0x44DF2800 #define CM_PER 0x44DF8800 +#define CM_DPLL 0x44DF4200 +#define CM_RTC 0x44DF8500
#define PRM_RSTCTRL (PRCM_BASE + 0x4000) #define PRM_RSTST (PRM_RSTCTRL + 4)