Emails to the board maintainer "Rishi Bhattacharya rishi@ti.com" have been bouncing.
Tom suggested to remove this board.
Remove also omap1510_udc.c because this is the last board to enable it.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com Suggested-by: Tom Rini trini@ti.com ---
arch/arm/Kconfig | 4 - board/ti/omap5912osk/Kconfig | 23 - board/ti/omap5912osk/MAINTAINERS | 6 - board/ti/omap5912osk/Makefile | 9 - board/ti/omap5912osk/config.mk | 30 - board/ti/omap5912osk/lowlevel_init.S | 477 ----------- board/ti/omap5912osk/omap5912osk.c | 307 ------- configs/omap5912osk_defconfig | 2 - doc/README.scrapyard | 1 + drivers/usb/gadget/Makefile | 1 - drivers/usb/gadget/omap1510_udc.c | 1506 ---------------------------------- include/configs/omap1510.h | 756 ----------------- include/configs/omap5912osk.h | 174 ---- 13 files changed, 1 insertion(+), 3295 deletions(-) delete mode 100644 board/ti/omap5912osk/Kconfig delete mode 100644 board/ti/omap5912osk/MAINTAINERS delete mode 100644 board/ti/omap5912osk/Makefile delete mode 100644 board/ti/omap5912osk/config.mk delete mode 100644 board/ti/omap5912osk/lowlevel_init.S delete mode 100644 board/ti/omap5912osk/omap5912osk.c delete mode 100644 configs/omap5912osk_defconfig delete mode 100644 drivers/usb/gadget/omap1510_udc.c delete mode 100644 include/configs/omap1510.h delete mode 100644 include/configs/omap5912osk.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e385eda..e97f94d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -287,9 +287,6 @@ config TARGET_SC_SPS_1 config TARGET_NHK8815 bool "Support nhk8815"
-config TARGET_OMAP5912OSK - bool "Support omap5912osk" - config TARGET_EDMINIV2 bool "Support edminiv2"
@@ -977,7 +974,6 @@ source "board/ti/beagle/Kconfig" source "board/ti/dra7xx/Kconfig" source "board/ti/evm/Kconfig" source "board/ti/ks2_evm/Kconfig" -source "board/ti/omap5912osk/Kconfig" source "board/ti/omap5_uevm/Kconfig" source "board/ti/panda/Kconfig" source "board/ti/sdp3430/Kconfig" diff --git a/board/ti/omap5912osk/Kconfig b/board/ti/omap5912osk/Kconfig deleted file mode 100644 index 9f7493a..0000000 --- a/board/ti/omap5912osk/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if TARGET_OMAP5912OSK - -config SYS_CPU - string - default "arm926ejs" - -config SYS_BOARD - string - default "omap5912osk" - -config SYS_VENDOR - string - default "ti" - -config SYS_SOC - string - default "omap" - -config SYS_CONFIG_NAME - string - default "omap5912osk" - -endif diff --git a/board/ti/omap5912osk/MAINTAINERS b/board/ti/omap5912osk/MAINTAINERS deleted file mode 100644 index 43ffb9b..0000000 --- a/board/ti/omap5912osk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -OMAP5912OSK BOARD -M: Rishi Bhattacharya rishi@ti.com -S: Maintained -F: board/ti/omap5912osk/ -F: include/configs/omap5912osk.h -F: configs/omap5912osk_defconfig diff --git a/board/ti/omap5912osk/Makefile b/board/ti/omap5912osk/Makefile deleted file mode 100644 index d7c0ebd..0000000 --- a/board/ti/omap5912osk/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := omap5912osk.o -obj-y += lowlevel_init.o diff --git a/board/ti/omap5912osk/config.mk b/board/ti/omap5912osk/config.mk deleted file mode 100644 index 5b8d952..0000000 --- a/board/ti/omap5912osk/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2002-2004 -# Gary Jennejohn, DENX Software Engineering, garyj@denx.de -# David Mueller, ELSOFT AG, d.mueller@elsoft.ch -# -# (C) Copyright 2003 -# Texas Instruments, <www.ti.com> -# Kshitij Gupta Kshitij@ti.com -# -# (C) Copyright 2004 -# Texas Instruments, <www.ti.com> -# Rishi Bhattacharya rishi@ti.com -# -# TI OSK board with OMAP5912 (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# OSK has 1 bank of 32 MB SDRAM -# Physical Address: -# 1000'0000 to 1200'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 -# (mem base + reserved) -# -# When running from RAM use address 1108'0000, otherwise when -# booting from NOR flash link to address 0000'0000. -# - -CONFIG_SYS_TEXT_BASE = 0x00000000 -#CONFIG_SYS_TEXT_BASE = 0x11080000 diff --git a/board/ti/omap5912osk/lowlevel_init.S b/board/ti/omap5912osk/lowlevel_init.S deleted file mode 100644 index e05a1c7..0000000 --- a/board/ti/omap5912osk/lowlevel_init.S +++ /dev/null @@ -1,477 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, <www.ti.com> - * Kshitij Gupta Kshitij@ti.com - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004 - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> - -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - -.globl lowlevel_init -lowlevel_init: - - /*------------------------------------------------------* - * Ensure i-cache is enabled * - * To configure TC regs without fetching instruction * - *------------------------------------------------------*/ - mrc p15, 0, r0, c1, c0 - orr r0, r0, #0x1000 - mcr p15, 0, r0, c1, c0 - - /*------------------------------------------------------* - *mask all IRQs by setting all bits in the INTMR default* - *------------------------------------------------------*/ - mov r1, #0xffffffff - ldr r0, =REG_IHL1_MIR - str r1, [r0] - ldr r0, =REG_IHL2_MIR - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT1) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT1 - ldr r1, VAL_ARM_IDLECT1 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT2 - ldr r1, VAL_ARM_IDLECT2 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT3) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT3 - ldr r1, VAL_ARM_IDLECT3 - str r1, [r0] - - mov r1, #0x01 /* PER_EN bit */ - ldr r0, REG_ARM_RSTCT2 - strh r1, [r0] /* CLKM; Peripheral reset. */ - - /* Set CLKM to Sync-Scalable */ - mov r1, #0x1000 - ldr r0, REG_ARM_SYSST - - mov r2, #0 -1: cmp r2, #1 - streqh r1, [r0] - add r2, r2, #1 - cmp r2, #0x100 /* wait for any bubbles to finish */ - bne 1b - - ldr r1, VAL_ARM_CKCTL - ldr r0, REG_ARM_CKCTL - strh r1, [r0] - - /* a few nops to let settle */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* setup DPLL 1 */ - /* Ramp up the clock to 96Mhz */ - ldr r1, VAL_DPLL1_CTL - ldr r0, REG_DPLL1_CTL - strh r1, [r0] - ands r1, r1, #0x10 /* Check if PLL is enabled. */ - beq lock_end /* Do not look for lock if BYPASS selected */ -2: - ldrh r1, [r0] - ands r1, r1, #0x01 /* Check the LOCK bit.*/ - beq 2b /* loop until bit goes hi. */ -lock_end: - - /*------------------------------------------------------* - * Turn off the watchdog during init... * - *------------------------------------------------------*/ - ldr r0, REG_WATCHDOG - ldr r1, WATCHDOG_VAL1 - str r1, [r0] - ldr r1, WATCHDOG_VAL2 - str r1, [r0] - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL1 - str r1, [r0] - ldr r0, REG_WWPSDOG - -watch1Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch1Wait - - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL2 - str r1, [r0] - ldr r0, REG_WWPSDOG -watch2Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch2Wait - - /* Set memory timings corresponding to the new clock speed */ - ldr r3, VAL_SDRAM_CONFIG_SDF0 - - /* Check execution location to determine current execution location - * and branch to appropriate initialization code. - */ - mov r0, #0x10000000 /* Load physical SDRAM base. */ - mov r1, pc /* Get current execution location. */ - cmp r1, r0 /* Compare. */ - bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */ - - /* identify the device revision, -- TMX or TMP(TMS) */ - ldr r0, REG_DEVICE_ID - ldr r1, [r0] - - ldr r0, VAL_DEVICE_ID_TMP - mov r1, r1, lsl #15 - mov r1, r1, lsr #16 - cmp r0, r1 - bne skip_TMP_Patch - - /* Enable TMP/TMS device new features */ - mov r0, #1 - ldr r1, REG_TC_EMIFF_DOUBLER - str r0, [r1] - - /* Enable new ac parameters */ - mov r0, #0x0b - ldr r1, REG_SDRAM_CONFIG2 - str r0, [r1] - - ldr r3, VAL_SDRAM_CONFIG_SDF1 - -skip_TMP_Patch: - - /* - * Delay for SDRAM initialization. - */ - mov r0, #0x1800 /* value should be checked */ -3: - subs r0, r0, #0x1 /* Decrement count */ - bne 3b - - /* - * Set SDRAM control values. Disable refresh before MRS command. - */ - - /* mobile ddr operation */ - ldr r0, REG_SDRAM_OPERATION - mov r2, #07 - str r2, [r0] - - /* config register */ - ldr r0, REG_SDRAM_CONFIG - str r3, [r0] - - /* manual command register */ - ldr r0, REG_SDRAM_MANUAL_CMD - - /* issue set cke high */ - mov r1, #CMD_SDRAM_CKE_SET_HIGH - str r1, [r0] - - /* issue nop */ - mov r1, #CMD_SDRAM_NOP - str r1, [r0] - - mov r2, #0x0100 -waitMDDR1: - subs r2, r2, #1 - bne waitMDDR1 /* delay loop */ - - /* issue precharge */ - mov r1, #CMD_SDRAM_PRECHARGE - str r1, [r0] - - /* issue autorefresh x 2 */ - mov r1, #CMD_SDRAM_AUTOREFRESH - str r1, [r0] - str r1, [r0] - - /* mrs register ddr mobile */ - ldr r0, REG_SDRAM_MRS - mov r1, #0x33 - str r1, [r0] - - /* emrs1 low-power register */ - ldr r0, REG_SDRAM_EMRS1 - /* self refresh on all banks */ - mov r1, #0 - str r1, [r0] - - ldr r0, REG_DLL_URD_CONTROL - ldr r1, DLL_URD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_LRD_CONTROL - ldr r1, DLL_LRD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_WRT_CONTROL - ldr r1, DLL_WRT_CONTROL_VAL - str r1, [r0] - - /* delay loop */ - mov r0, #0x0100 -waitMDDR2: - subs r0, r0, #1 - bne waitMDDR2 - - /* - * Delay for SDRAM initialization. - */ - mov r0, #0x1800 -4: - subs r0, r0, #1 /* Decrement count. */ - bne 4b - b common_tc - -skip_sdram: - ldr r0, REG_SDRAM_CONFIG - str r3, [r0] - -common_tc: - /* slow interface */ - ldr r1, VAL_TC_EMIFS_CS0_CONFIG - ldr r0, REG_TC_EMIFS_CS0_CONFIG - str r1, [r0] /* Chip Select 0 */ - - ldr r1, VAL_TC_EMIFS_CS1_CONFIG - ldr r0, REG_TC_EMIFS_CS1_CONFIG - str r1, [r0] /* Chip Select 1 */ - - ldr r1, VAL_TC_EMIFS_CS3_CONFIG - ldr r0, REG_TC_EMIFS_CS3_CONFIG - str r1, [r0] /* Chip Select 3 */ - - ldr r1, VAL_TC_EMIFS_DWS - ldr r0, REG_TC_EMIFS_DWS - str r1, [r0] /* Enable EMIFS.RDY for CS1 (ether) */ - -#ifdef CONFIG_H2_OMAP1610 - /* inserting additional 2 clock cycle hold time for LAN */ - ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED - str r1, [r0] -#endif - /* Start MPU Timer 1 */ - ldr r0, REG_MPU_LOAD_TIMER - ldr r1, VAL_MPU_LOAD_TIMER - str r1, [r0] - - ldr r0, REG_MPU_CNTL_TIMER - ldr r1, VAL_MPU_CNTL_TIMER - str r1, [r0] - - /* - * Setup a temporary stack - */ - ldr sp, SRAM_STACK - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - - /* - * Save the old lr(passed in ip) and the current lr to stack - */ - push {ip, lr} - - /* - * go setup pll, mux, memory - */ - bl s_init - pop {ip, pc} - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_DEVICE_ID: /* 32 bits */ - .word 0xfffe2004 -REG_TC_EMIFS_CONFIG: - .word 0xfffecc0c -REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ - .word 0xfffecc10 -REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ - .word 0xfffecc14 -REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ - .word 0xfffecc18 -REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ - .word 0xfffecc1c -REG_TC_EMIFS_DWS: /* 32 bits */ - .word 0xfffecc40 -#ifdef CONFIG_H2_OMAP1610 -REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ - .word 0xfffecc54 -#endif - -/* MPU clock/reset/power mode control registers */ -REG_ARM_CKCTL: /* 16 bits */ - .word 0xfffece00 -REG_ARM_IDLECT3: /* 16 bits */ - .word 0xfffece24 -REG_ARM_IDLECT2: /* 16 bits */ - .word 0xfffece08 -REG_ARM_IDLECT1: /* 16 bits */ - .word 0xfffece04 -REG_ARM_RSTCT2: /* 16 bits */ - .word 0xfffece14 -REG_ARM_SYSST: /* 16 bits */ - .word 0xfffece18 - -/* DPLL control registers */ -REG_DPLL1_CTL: /* 16 bits */ - .word 0xfffecf00 - -/* Watch Dog register */ -/* secure watchdog stop */ -REG_WSPRDOG: - .word 0xfffeb048 -/* watchdog write pending */ -REG_WWPSDOG: - .word 0xfffeb034 - -WSPRDOG_VAL1: - .word 0x0000aaaa -WSPRDOG_VAL2: - .word 0x00005555 - -/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, - counter @8192 rows, 10 ns, 8 burst */ -REG_SDRAM_CONFIG: - .word 0xfffecc20 -REG_SDRAM_CONFIG2: - .word 0xfffecc3c -REG_TC_EMIFF_DOUBLER: /* 32 bits */ - .word 0xfffecc60 - -/* Operation register */ -REG_SDRAM_OPERATION: - .word 0xfffecc80 - -/* Manual command register */ -REG_SDRAM_MANUAL_CMD: - .word 0xfffecc84 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_MRS: - .word 0xfffecc70 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_EMRS1: - .word 0xfffecc78 - -/* WRT DLL register */ -REG_DLL_WRT_CONTROL: - .word 0xfffecc68 -DLL_WRT_CONTROL_VAL: - .word 0x03f00002 /* Phase of 72deg, write offset +31 */ - -/* URD DLL register */ -REG_DLL_URD_CONTROL: - .word 0xfffeccc0 -DLL_URD_CONTROL_VAL: - .word 0x00800002 /* Phase of 72deg, read offset +31 */ - -/* LRD DLL register */ -REG_DLL_LRD_CONTROL: - .word 0xfffecccc -DLL_LRD_CONTROL_VAL: - .word 0x00800002 /* read offset +31 */ - -REG_WATCHDOG: - .word 0xfffec808 -WATCHDOG_VAL1: - .word 0x000000f5 -WATCHDOG_VAL2: - .word 0x000000a0 - -REG_MPU_LOAD_TIMER: - .word 0xfffec504 -REG_MPU_CNTL_TIMER: - .word 0xfffec500 -VAL_MPU_LOAD_TIMER: - .word 0xffffffff -VAL_MPU_CNTL_TIMER: - .word 0xffffffa1 - -/* 96 MHz Samsung Mobile DDR */ -/* Original setting for TMX device */ -VAL_SDRAM_CONFIG_SDF0: - .word 0x0014e6fe - -/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */ -VAL_SDRAM_CONFIG_SDF1: - .word 0x0114e6fe - -VAL_ARM_CKCTL: - .word 0x2000 /* was: 0x3000, now use CLK_REF for timer input */ -VAL_DPLL1_CTL: - .word 0x2830 - -#ifdef CONFIG_OSK_OMAP5912 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x002130b0 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x00001133 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0x000055f0 -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88013141 -VAL_TC_EMIFS_DWS: /* Enable EMIFS.RDY for CS1 access (ether) */ - .word 0x000000c0 -VAL_DEVICE_ID_TMP: /* TMP/TMS=0xb65f, TMX=0xb58c */ - .word 0xb65f -#endif - -#ifdef CONFIG_H2_OMAP1610 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x00203331 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x8180fff3 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0xf800f22a -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88013141 -VAL_TC_EMIFS_CS1_ADVANCED: - .word 0x00000022 -#endif - -VAL_ARM_IDLECT1: - .word 0x00000400 -VAL_ARM_IDLECT2: - .word 0x00000886 -VAL_ARM_IDLECT3: - .word 0x00000015 - -SRAM_STACK: - .word CONFIG_SYS_INIT_SP_ADDR - -/* command values */ -.equ CMD_SDRAM_NOP, 0x00000000 -.equ CMD_SDRAM_PRECHARGE, 0x00000001 -.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 -.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 diff --git a/board/ti/omap5912osk/omap5912osk.c b/board/ti/omap5912osk/omap5912osk.c deleted file mode 100644 index 88a7310..0000000 --- a/board/ti/omap5912osk/omap5912osk.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * (C) Copyright 2003 - * Texas Instruments, <www.ti.com> - * Kshitij Gupta Kshitij@ti.com - * - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Rishi Bhattacharya rishi@ti.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -void flash__init (void); -void ether__init (void); -void set_muxconf_regs (void); -void peripheral_power_enable (void); - -#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - flash__init(); - ether__init(); - - return 0; -} - -void s_init(void) -{ - /* Configure MUX settings */ - set_muxconf_regs (); - peripheral_power_enable (); - -/* this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ -#define EMIFS_GlB_Config_REG 0xfffecc0c - unsigned int regval; - regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); - /* Turn off write protection for flash devices. */ - regval = regval | 0x0001; - *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -#define ETH_CONTROL_REG 0x0480000b - int i; - - *((volatile unsigned short *) 0xfffece08) = 0x03FF; - *((volatile unsigned short *) 0xfffb3824) = 0x8000; - *((volatile unsigned short *) 0xfffb3830) = 0x0000; - *((volatile unsigned short *) 0xfffb3834) = 0x0009; - *((volatile unsigned short *) 0xfffb3838) = 0x0009; - *((volatile unsigned short *) 0xfffb3818) = 0x0002; - *((volatile unsigned short *) 0xfffb382C) = 0x0048; - *((volatile unsigned short *) 0xfffb3824) = 0x8603; - udelay (3); - for (i=0;i<2000;i++); - *((volatile unsigned short *) 0xfffb381C) = 0x6610; - udelay (30); - for (i=0;i<10000;i++); - - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (3); - - -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -/****************************************************** - Routine: set_muxconf_regs - Description: Setting up the configuration Mux registers - specific to the hardware -*******************************************************/ -void set_muxconf_regs (void) -{ - volatile unsigned int *MuxConfReg; - /* set each registers to its reset value; */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* setup for UART1 */ - *MuxConfReg &= ~(0x02000000); /* bit 25 */ - /* setup for UART2 */ - *MuxConfReg &= ~(0x01000000); /* bit 24 */ - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x08000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6); - /*setup mux for UART3 */ - *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */ - *MuxConfReg &= ~0x0000003e; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8); - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9); - /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */ - /* hardware will actually use TX and RTS based on bit 25 in */ - /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */ - *MuxConfReg |= 0x00201000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C); - /* setup for UART2 */ - /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */ - /* hardware will actually use TX and RTS based on bit 24 in */ - /* FUNC_MUX_CTRL_0. */ - *MuxConfReg |= 0x09000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_D); - *MuxConfReg |= 0x00000020; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1); - *MuxConfReg = 0x00000000; - /* mux setup for SD/MMC driver */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2); - *MuxConfReg &= 0xFFFE0FFF; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 13 for MMC2 XOR_CLK */ - *MuxConfReg &= ~(0x00002000); - /* bit 29 for UART 1 */ - *MuxConfReg &= ~(0x00002000); - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */ - *MuxConfReg |= 0x000C0000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL); - *MuxConfReg &= ~(0x00000070); - *MuxConfReg &= ~(0x00000008); - *MuxConfReg |= 0x00000003; - *MuxConfReg |= 0x00000180; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 17, software controls VBUS */ - *MuxConfReg &= ~(0x00020000); - /* Enable USB 48 and 12M clocks */ - *MuxConfReg |= 0x00000200; - *MuxConfReg &= ~(0x00000180); - /*2.75V for MMCSDIO1 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0); - *MuxConfReg = 0x00001FE7; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4); - *MuxConfReg = 0x00000000; - /* Turn on UART2 48 MHZ clock */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - *MuxConfReg |= 0x40000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL); - /* setup for USB VBus detection OMAP161x */ - *MuxConfReg |= 0x00040000; /* bit 18 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - /* PullUps for SD/MMC driver */ - *MuxConfReg |= ~(0xFFFE0FFF); - MuxConfReg = - (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); - *MuxConfReg = COMP_MODE_ENABLE; -} - -/****************************************************** - Routine: peripheral_power_enable - Description: Enable the power for UART1 -*******************************************************/ -void peripheral_power_enable (void) -{ -#define UART1_48MHZ_ENABLE ((unsigned short)0x0200) -#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834) - - *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: OSK5912"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/configs/omap5912osk_defconfig b/configs/omap5912osk_defconfig deleted file mode 100644 index 5aeb097..0000000 --- a/configs/omap5912osk_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_OMAP5912OSK=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index b950a41..6f28ab0 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +omap5912osk arm arm926ejs - - Rishi Bhattacharya rishi@ti.com p1023rds powerpc mpc85xx d0bc5140 2014-07-22 Roy Zang tie-fei.zang@freescale.com spc1920 powerpc mpc8xx 98ad54be 2014-07-07 v37 powerpc mpc8xx b8c1438a 2014-07-07 diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 4eea907..2efd5a4 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -31,7 +31,6 @@ ifdef CONFIG_USB_DEVICE obj-y += core.o obj-y += ep0.o obj-$(CONFIG_DW_UDC) += designware_udc.o -obj-$(CONFIG_OMAP1610) += omap1510_udc.o obj-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o obj-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o endif diff --git a/drivers/usb/gadget/omap1510_udc.c b/drivers/usb/gadget/omap1510_udc.c deleted file mode 100644 index 959df8c..0000000 --- a/drivers/usb/gadget/omap1510_udc.c +++ /dev/null @@ -1,1506 +0,0 @@ -/* - * (C) Copyright 2003 - * Gerry Hamel, geh@ti.com, Texas Instruments - * - * Based on - * linux/drivers/usb/device/bi/omap.c - * TI OMAP1510 USB bus interface driver - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * (C) Copyright 2002 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <usbdevice.h> -#include <usb/omap1510_udc.h> -#include <usb/udc.h> - -#include "ep0.h" - - -#define UDC_INIT_MDELAY 80 /* Device settle delay */ -#define UDC_MAX_ENDPOINTS 31 /* Number of endpoints on this UDC */ - -/* Some kind of debugging output... */ -#if 1 -#define UDCDBG(str) -#define UDCDBGA(fmt,args...) -#else /* The bugs still exists... */ -#define UDCDBG(str) serial_printf("[%s] %s:%d: " str "\n", __FILE__,__FUNCTION__,__LINE__) -#define UDCDBGA(fmt,args...) serial_printf("[%s] %s:%d: " fmt "\n", __FILE__,__FUNCTION__,__LINE__, ##args) -#endif - -#if 1 -#define UDCREG(name) -#define UDCREGL(name) -#else /* The bugs still exists... */ -#define UDCREG(name) serial_printf("%s():%d: %s[%08x]=%.4x\n",__FUNCTION__,__LINE__, (#name), name, inw(name)) /* For 16-bit regs */ -#define UDCREGL(name) serial_printf("%s():%d: %s[%08x]=%.8x\n",__FUNCTION__,__LINE__, (#name), name, inl(name)) /* For 32-bit regs */ -#endif - - -static struct urb *ep0_urb = NULL; - -static struct usb_device_instance *udc_device; /* Used in interrupt handler */ -static u16 udc_devstat = 0; /* UDC status (DEVSTAT) */ -static u32 udc_interrupts = 0; - -static void udc_stall_ep (unsigned int ep_addr); - - -static struct usb_endpoint_instance *omap1510_find_ep (int ep) -{ - int i; - - for (i = 0; i < udc_device->bus->max_endpoints; i++) { - if (udc_device->bus->endpoint_array[i].endpoint_address == ep) - return &udc_device->bus->endpoint_array[i]; - } - return NULL; -} - -/* ************************************************************************** */ -/* IO - */ - -/* - * omap1510_prepare_endpoint_for_rx - * - * This function implements TRM Figure 14-11. - * - * The endpoint to prepare for transfer is specified as a physical endpoint - * number. For OUT (rx) endpoints 1 through 15, the corresponding endpoint - * configuration register is checked to see if the endpoint is ISO or not. - * If the OUT endpoint is valid and is non-ISO then its FIFO is enabled. - * No action is taken for endpoint 0 or for IN (tx) endpoints 16 through 30. - */ -static void omap1510_prepare_endpoint_for_rx (int ep_addr) -{ - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - - UDCDBGA ("omap1510_prepare_endpoint %x", ep_addr); - if (((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT)) { - if ((inw (UDC_EP_RX (ep_num)) & - (UDC_EPn_RX_Valid | UDC_EPn_RX_Iso)) == - UDC_EPn_RX_Valid) { - /* rx endpoint is valid, non-ISO, so enable its FIFO */ - outw (UDC_EP_Sel | ep_num, UDC_EP_NUM); - outw (UDC_Set_FIFO_En, UDC_CTRL); - outw (0, UDC_EP_NUM); - } - } -} - -/* omap1510_configure_endpoints - * - * This function implements TRM Figure 14-10. - */ -static void omap1510_configure_endpoints (struct usb_device_instance *device) -{ - int ep; - struct usb_bus_instance *bus; - struct usb_endpoint_instance *endpoint; - unsigned short ep_ptr; - unsigned short ep_size; - unsigned short ep_isoc; - unsigned short ep_doublebuffer; - int ep_addr; - int packet_size; - int buffer_size; - int attributes; - - bus = device->bus; - - /* There is a dedicated 2048 byte buffer for USB packets that may be - * arbitrarily partitioned among the endpoints on 8-byte boundaries. - * The first 8 bytes are reserved for receiving setup packets on - * endpoint 0. - */ - ep_ptr = 8; /* reserve the first 8 bytes for the setup fifo */ - - for (ep = 0; ep < bus->max_endpoints; ep++) { - endpoint = bus->endpoint_array + ep; - ep_addr = endpoint->endpoint_address; - if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - /* IN endpoint */ - packet_size = endpoint->tx_packetSize; - attributes = endpoint->tx_attributes; - } else { - /* OUT endpoint */ - packet_size = endpoint->rcv_packetSize; - attributes = endpoint->rcv_attributes; - } - - switch (packet_size) { - case 0: - ep_size = 0; - break; - case 8: - ep_size = 0; - break; - case 16: - ep_size = 1; - break; - case 32: - ep_size = 2; - break; - case 64: - ep_size = 3; - break; - case 128: - ep_size = 4; - break; - case 256: - ep_size = 5; - break; - case 512: - ep_size = 6; - break; - default: - UDCDBGA ("ep 0x%02x has bad packet size %d", - ep_addr, packet_size); - packet_size = 0; - ep_size = 0; - break; - } - - switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) { - case USB_ENDPOINT_XFER_CONTROL: - case USB_ENDPOINT_XFER_BULK: - case USB_ENDPOINT_XFER_INT: - default: - /* A non-isochronous endpoint may optionally be - * double-buffered. For now we disable - * double-buffering. - */ - ep_doublebuffer = 0; - ep_isoc = 0; - if (packet_size > 64) - packet_size = 0; - if (!ep || !ep_doublebuffer) - buffer_size = packet_size; - else - buffer_size = packet_size * 2; - break; - case USB_ENDPOINT_XFER_ISOC: - /* Isochronous endpoints are always double- - * buffered, but the double-buffering bit - * in the endpoint configuration register - * becomes the msb of the endpoint size so we - * set the double-buffering flag to zero. - */ - ep_doublebuffer = 0; - ep_isoc = 1; - buffer_size = packet_size * 2; - break; - } - - /* check to see if our packet buffer RAM is exhausted */ - if ((ep_ptr + buffer_size) > 2048) { - UDCDBGA ("out of packet RAM for ep 0x%02x buf size %d", ep_addr, buffer_size); - buffer_size = packet_size = 0; - } - - /* force a default configuration for endpoint 0 since it is - * always enabled - */ - if (!ep && ((packet_size < 8) || (packet_size > 64))) { - buffer_size = packet_size = 64; - ep_size = 3; - } - - if (!ep) { - /* configure endpoint 0 */ - outw ((ep_size << 12) | (ep_ptr >> 3), UDC_EP0); - /*UDCDBGA("ep 0 buffer offset 0x%03x packet size 0x%03x", */ - /* ep_ptr, packet_size); */ - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - /* IN endpoint */ - if (packet_size) { - outw ((1 << 15) | (ep_doublebuffer << 14) | - (ep_size << 12) | (ep_isoc << 11) | - (ep_ptr >> 3), - UDC_EP_TX (ep_addr & - USB_ENDPOINT_NUMBER_MASK)); - UDCDBGA ("IN ep %d buffer offset 0x%03x" - " packet size 0x%03x", - ep_addr & USB_ENDPOINT_NUMBER_MASK, - ep_ptr, packet_size); - } else { - outw (0, - UDC_EP_TX (ep_addr & - USB_ENDPOINT_NUMBER_MASK)); - } - } else { - /* OUT endpoint */ - if (packet_size) { - outw ((1 << 15) | (ep_doublebuffer << 14) | - (ep_size << 12) | (ep_isoc << 11) | - (ep_ptr >> 3), - UDC_EP_RX (ep_addr & - USB_ENDPOINT_NUMBER_MASK)); - UDCDBGA ("OUT ep %d buffer offset 0x%03x" - " packet size 0x%03x", - ep_addr & USB_ENDPOINT_NUMBER_MASK, - ep_ptr, packet_size); - } else { - outw (0, - UDC_EP_RX (ep_addr & - USB_ENDPOINT_NUMBER_MASK)); - } - } - ep_ptr += buffer_size; - } -} - -/* omap1510_deconfigure_device - * - * This function balances omap1510_configure_device. - */ -static void omap1510_deconfigure_device (void) -{ - int epnum; - - UDCDBG ("clear Cfg_Lock"); - outw (inw (UDC_SYSCON1) & ~UDC_Cfg_Lock, UDC_SYSCON1); - UDCREG (UDC_SYSCON1); - - /* deconfigure all endpoints */ - for (epnum = 1; epnum <= 15; epnum++) { - outw (0, UDC_EP_RX (epnum)); - outw (0, UDC_EP_TX (epnum)); - } -} - -/* omap1510_configure_device - * - * This function implements TRM Figure 14-9. - */ -static void omap1510_configure_device (struct usb_device_instance *device) -{ - omap1510_configure_endpoints (device); - - - /* Figure 14-9 indicates we should enable interrupts here, but we have - * other routines (udc_all_interrupts, udc_suspended_interrupts) to - * do that. - */ - - UDCDBG ("set Cfg_Lock"); - outw (inw (UDC_SYSCON1) | UDC_Cfg_Lock, UDC_SYSCON1); - UDCREG (UDC_SYSCON1); -} - -/* omap1510_write_noniso_tx_fifo - * - * This function implements TRM Figure 14-30. - * - * If the endpoint has an active tx_urb, then the next packet of data from the - * URB is written to the tx FIFO. The total amount of data in the urb is given - * by urb->actual_length. The maximum amount of data that can be sent in any - * one packet is given by endpoint->tx_packetSize. The number of data bytes - * from this URB that have already been transmitted is given by endpoint->sent. - * endpoint->last is updated by this routine with the number of data bytes - * transmitted in this packet. - * - * In accordance with Figure 14-30, the EP_NUM register must already have been - * written with the value to select the appropriate tx FIFO before this routine - * is called. - */ -static void omap1510_write_noniso_tx_fifo (struct usb_endpoint_instance - *endpoint) -{ - struct urb *urb = endpoint->tx_urb; - - if (urb) { - unsigned int last, i; - - UDCDBGA ("urb->buffer %p, buffer_length %d, actual_length %d", - urb->buffer, urb->buffer_length, urb->actual_length); - if ((last = - MIN (urb->actual_length - endpoint->sent, - endpoint->tx_packetSize))) { - u8 *cp = urb->buffer + endpoint->sent; - - UDCDBGA ("endpoint->sent %d, tx_packetSize %d, last %d", endpoint->sent, endpoint->tx_packetSize, last); - - if (((u32) cp & 1) == 0) { /* word aligned? */ - outsw (UDC_DATA, cp, last >> 1); - } else { /* byte aligned. */ - for (i = 0; i < (last >> 1); i++) { - u16 w = ((u16) cp[2 * i + 1] << 8) | - (u16) cp[2 * i]; - outw (w, UDC_DATA); - } - } - if (last & 1) { - outb (*(cp + last - 1), UDC_DATA); - } - } - endpoint->last = last; - } -} - -/* omap1510_read_noniso_rx_fifo - * - * This function implements TRM Figure 14-28. - * - * If the endpoint has an active rcv_urb, then the next packet of data is read - * from the rcv FIFO and written to rcv_urb->buffer at offset - * rcv_urb->actual_length to append the packet data to the data from any - * previous packets for this transfer. We assume that there is sufficient room - * left in the buffer to hold an entire packet of data. - * - * The return value is the number of bytes read from the FIFO for this packet. - * - * In accordance with Figure 14-28, the EP_NUM register must already have been - * written with the value to select the appropriate rcv FIFO before this routine - * is called. - */ -static int omap1510_read_noniso_rx_fifo (struct usb_endpoint_instance - *endpoint) -{ - struct urb *urb = endpoint->rcv_urb; - int len = 0; - - if (urb) { - len = inw (UDC_RXFSTAT); - - if (len) { - unsigned char *cp = urb->buffer + urb->actual_length; - - insw (UDC_DATA, cp, len >> 1); - if (len & 1) - *(cp + len - 1) = inb (UDC_DATA); - } - } - return len; -} - -/* omap1510_prepare_for_control_write_status - * - * This function implements TRM Figure 14-17. - * - * We have to deal here with non-autodecoded control writes that haven't already - * been dealt with by ep0_recv_setup. The non-autodecoded standard control - * write requests are: set/clear endpoint feature, set configuration, set - * interface, and set descriptor. ep0_recv_setup handles set/clear requests for - * ENDPOINT_HALT by halting the endpoint for a set request and resetting the - * endpoint for a clear request. ep0_recv_setup returns an error for - * SET_DESCRIPTOR requests which causes them to be terminated with a stall by - * the setup handler. A SET_INTERFACE request is handled by ep0_recv_setup by - * generating a DEVICE_SET_INTERFACE event. This leaves only the - * SET_CONFIGURATION event for us to deal with here. - * - */ -static void omap1510_prepare_for_control_write_status (struct urb *urb) -{ - struct usb_device_request *request = &urb->device_request;; - - /* check for a SET_CONFIGURATION request */ - if (request->bRequest == USB_REQ_SET_CONFIGURATION) { - int configuration = le16_to_cpu (request->wValue) & 0xff; - unsigned short devstat = inw (UDC_DEVSTAT); - - if ((devstat & (UDC_ADD | UDC_CFG)) == UDC_ADD) { - /* device is currently in ADDRESSED state */ - if (configuration) { - /* Assume the specified non-zero configuration - * value is valid and switch to the CONFIGURED - * state. - */ - outw (UDC_Dev_Cfg, UDC_SYSCON2); - } - } else if ((devstat & UDC_CFG) == UDC_CFG) { - /* device is currently in CONFIGURED state */ - if (!configuration) { - /* Switch to ADDRESSED state. */ - outw (UDC_Clr_Cfg, UDC_SYSCON2); - } - } - } - - /* select EP0 tx FIFO */ - outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); - /* clear endpoint (no data bytes in status stage) */ - outw (UDC_Clr_EP, UDC_CTRL); - /* enable the EP0 tx FIFO */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect the endpoint */ - outw (UDC_EP_Dir, UDC_EP_NUM); -} - -/* udc_state_transition_up - * udc_state_transition_down - * - * Helper functions to implement device state changes. The device states and - * the events that transition between them are: - * - * STATE_ATTACHED - * || /\ - * / || - * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET - * || /\ - * / || - * STATE_POWERED - * || /\ - * / || - * DEVICE_RESET DEVICE_POWER_INTERRUPTION - * || /\ - * / || - * STATE_DEFAULT - * || /\ - * / || - * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET - * || /\ - * / || - * STATE_ADDRESSED - * || /\ - * / || - * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED - * || /\ - * / || - * STATE_CONFIGURED - * - * udc_state_transition_up transitions up (in the direction from STATE_ATTACHED - * to STATE_CONFIGURED) from the specified initial state to the specified final - * state, passing through each intermediate state on the way. If the initial - * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then - * no state transitions will take place. - * - * udc_state_transition_down transitions down (in the direction from - * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the - * specified final state, passing through each intermediate state on the way. - * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final - * state, then no state transitions will take place. - * - * These functions must only be called with interrupts disabled. - */ -static void udc_state_transition_up (usb_device_state_t initial, - usb_device_state_t final) -{ - if (initial < final) { - switch (initial) { - case STATE_ATTACHED: - usbd_device_event_irq (udc_device, - DEVICE_HUB_CONFIGURED, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq (udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq (udc_device, - DEVICE_ADDRESS_ASSIGNED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq (udc_device, DEVICE_CONFIGURED, - 0); - case STATE_CONFIGURED: - break; - default: - break; - } - } -} - -static void udc_state_transition_down (usb_device_state_t initial, - usb_device_state_t final) -{ - if (initial > final) { - switch (initial) { - case STATE_CONFIGURED: - usbd_device_event_irq (udc_device, DEVICE_DE_CONFIGURED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq (udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq (udc_device, DEVICE_POWER_INTERRUPTION, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq (udc_device, DEVICE_HUB_RESET, 0); - case STATE_ATTACHED: - break; - default: - break; - } - } -} - -/* Handle all device state changes. - * This function implements TRM Figure 14-21. - */ -static void omap1510_udc_state_changed (void) -{ - u16 bits; - u16 devstat = inw (UDC_DEVSTAT); - - UDCDBGA ("state changed, devstat %x, old %x", devstat, udc_devstat); - - bits = devstat ^ udc_devstat; - if (bits) { - if (bits & UDC_ATT) { - if (devstat & UDC_ATT) { - UDCDBG ("device attached and powered"); - udc_state_transition_up (udc_device->device_state, STATE_POWERED); - } else { - UDCDBG ("device detached or unpowered"); - udc_state_transition_down (udc_device->device_state, STATE_ATTACHED); - } - } - if (bits & UDC_USB_Reset) { - if (devstat & UDC_USB_Reset) { - UDCDBG ("device reset in progess"); - udc_state_transition_down (udc_device->device_state, STATE_POWERED); - } else { - UDCDBG ("device reset completed"); - } - } - if (bits & UDC_DEF) { - if (devstat & UDC_DEF) { - UDCDBG ("device entering default state"); - udc_state_transition_up (udc_device->device_state, STATE_DEFAULT); - } else { - UDCDBG ("device leaving default state"); - udc_state_transition_down (udc_device->device_state, STATE_POWERED); - } - } - if (bits & UDC_SUS) { - if (devstat & UDC_SUS) { - UDCDBG ("entering suspended state"); - usbd_device_event_irq (udc_device, DEVICE_BUS_INACTIVE, 0); - } else { - UDCDBG ("leaving suspended state"); - usbd_device_event_irq (udc_device, DEVICE_BUS_ACTIVITY, 0); - } - } - if (bits & UDC_R_WK_OK) { - UDCDBGA ("remote wakeup %s", (devstat & UDC_R_WK_OK) - ? "enabled" : "disabled"); - } - if (bits & UDC_ADD) { - if (devstat & UDC_ADD) { - UDCDBG ("default -> addressed"); - udc_state_transition_up (udc_device->device_state, STATE_ADDRESSED); - } else { - UDCDBG ("addressed -> default"); - udc_state_transition_down (udc_device->device_state, STATE_DEFAULT); - } - } - if (bits & UDC_CFG) { - if (devstat & UDC_CFG) { - UDCDBG ("device configured"); - /* The ep0_recv_setup function generates the - * DEVICE_CONFIGURED event when a - * USB_REQ_SET_CONFIGURATION setup packet is - * received, so we should already be in the - * state STATE_CONFIGURED. - */ - udc_state_transition_up (udc_device->device_state, STATE_CONFIGURED); - } else { - UDCDBG ("device deconfigured"); - udc_state_transition_down (udc_device->device_state, STATE_ADDRESSED); - } - } - } - - /* Clear interrupt source */ - outw (UDC_DS_Chg, UDC_IRQ_SRC); - - /* Save current DEVSTAT */ - udc_devstat = devstat; -} - -/* Handle SETUP USB interrupt. - * This function implements TRM Figure 14-14. - */ -static void omap1510_udc_setup (struct usb_endpoint_instance *endpoint) -{ - UDCDBG ("-> Entering device setup"); - - do { - const int setup_pktsize = 8; - unsigned char *datap = - (unsigned char *) &ep0_urb->device_request; - - /* Gain access to EP 0 setup FIFO */ - outw (UDC_Setup_Sel, UDC_EP_NUM); - - /* Read control request data */ - insb (UDC_DATA, datap, setup_pktsize); - - UDCDBGA ("EP0 setup read [%x %x %x %x %x %x %x %x]", - *(datap + 0), *(datap + 1), *(datap + 2), - *(datap + 3), *(datap + 4), *(datap + 5), - *(datap + 6), *(datap + 7)); - - /* Reset EP0 setup FIFO */ - outw (0, UDC_EP_NUM); - } while (inw (UDC_IRQ_SRC) & UDC_Setup); - - /* Try to process setup packet */ - if (ep0_recv_setup (ep0_urb)) { - /* Not a setup packet, stall next EP0 transaction */ - udc_stall_ep (0); - UDCDBG ("can't parse setup packet, still waiting for setup"); - return; - } - - /* Check direction */ - if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) - == USB_REQ_HOST2DEVICE) { - UDCDBG ("control write on EP0"); - if (le16_to_cpu (ep0_urb->device_request.wLength)) { - /* We don't support control write data stages. - * The only standard control write request with a data - * stage is SET_DESCRIPTOR, and ep0_recv_setup doesn't - * support that so we just stall those requests. A - * function driver might support a non-standard - * write request with a data stage, but it isn't - * obvious what we would do with the data if we read it - * so we'll just stall it. It seems like the API isn't - * quite right here. - */ -#if 0 - /* Here is what we would do if we did support control - * write data stages. - */ - ep0_urb->actual_length = 0; - outw (0, UDC_EP_NUM); - /* enable the EP0 rx FIFO */ - outw (UDC_Set_FIFO_En, UDC_CTRL); -#else - /* Stall this request */ - UDCDBG ("Stalling unsupported EP0 control write data " - "stage."); - udc_stall_ep (0); -#endif - } else { - omap1510_prepare_for_control_write_status (ep0_urb); - } - } else { - UDCDBG ("control read on EP0"); - /* The ep0_recv_setup function has already placed our response - * packet data in ep0_urb->buffer and the packet length in - * ep0_urb->actual_length. - */ - endpoint->tx_urb = ep0_urb; - endpoint->sent = 0; - /* select the EP0 tx FIFO */ - outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); - /* Write packet data to the FIFO. omap1510_write_noniso_tx_fifo - * will update endpoint->last with the number of bytes written - * to the FIFO. - */ - omap1510_write_noniso_tx_fifo (endpoint); - /* enable the FIFO to start the packet transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect the EP0 tx FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } - - UDCDBG ("<- Leaving device setup"); -} - -/* Handle endpoint 0 RX interrupt - * This routine implements TRM Figure 14-16. - */ -static void omap1510_udc_ep0_rx (struct usb_endpoint_instance *endpoint) -{ - unsigned short status; - - UDCDBG ("RX on EP0"); - /* select EP0 rx FIFO */ - outw (UDC_EP_Sel, UDC_EP_NUM); - - status = inw (UDC_STAT_FLG); - - if (status & UDC_ACK) { - /* Check direction */ - if ((ep0_urb->device_request.bmRequestType - & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) { - /* This rx interrupt must be for a control write data - * stage packet. - * - * We don't support control write data stages. - * We should never end up here. - */ - - /* clear the EP0 rx FIFO */ - outw (UDC_Clr_EP, UDC_CTRL); - - /* deselect the EP0 rx FIFO */ - outw (0, UDC_EP_NUM); - - UDCDBG ("Stalling unexpected EP0 control write " - "data stage packet"); - udc_stall_ep (0); - } else { - /* This rx interrupt must be for a control read status - * stage packet. - */ - UDCDBG ("ACK on EP0 control read status stage packet"); - /* deselect EP0 rx FIFO */ - outw (0, UDC_EP_NUM); - } - } else if (status & UDC_STALL) { - UDCDBG ("EP0 stall during RX"); - /* deselect EP0 rx FIFO */ - outw (0, UDC_EP_NUM); - } else { - /* deselect EP0 rx FIFO */ - outw (0, UDC_EP_NUM); - } -} - -/* Handle endpoint 0 TX interrupt - * This routine implements TRM Figure 14-18. - */ -static void omap1510_udc_ep0_tx (struct usb_endpoint_instance *endpoint) -{ - unsigned short status; - struct usb_device_request *request = &ep0_urb->device_request; - - UDCDBG ("TX on EP0"); - /* select EP0 TX FIFO */ - outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); - - status = inw (UDC_STAT_FLG); - if (status & UDC_ACK) { - /* Check direction */ - if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) == - USB_REQ_HOST2DEVICE) { - /* This tx interrupt must be for a control write status - * stage packet. - */ - UDCDBG ("ACK on EP0 control write status stage packet"); - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } else { - /* This tx interrupt must be for a control read data - * stage packet. - */ - int wLength = le16_to_cpu (request->wLength); - - /* Update our count of bytes sent so far in this - * transfer. - */ - endpoint->sent += endpoint->last; - - /* We are finished with this transfer if we have sent - * all of the bytes in our tx urb (urb->actual_length) - * unless we need a zero-length terminating packet. We - * need a zero-length terminating packet if we returned - * fewer bytes than were requested (wLength) by the host, - * and the number of bytes we returned is an exact - * multiple of the packet size endpoint->tx_packetSize. - */ - if ((endpoint->sent == ep0_urb->actual_length) - && ((ep0_urb->actual_length == wLength) - || (endpoint->last != - endpoint->tx_packetSize))) { - /* Done with control read data stage. */ - UDCDBG ("control read data stage complete"); - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - /* select EP0 RX FIFO to prepare for control - * read status stage. - */ - outw (UDC_EP_Sel, UDC_EP_NUM); - /* clear the EP0 RX FIFO */ - outw (UDC_Clr_EP, UDC_CTRL); - /* enable the EP0 RX FIFO */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect the EP0 RX FIFO */ - outw (0, UDC_EP_NUM); - } else { - /* We still have another packet of data to send - * in this control read data stage or else we - * need a zero-length terminating packet. - */ - UDCDBG ("ACK control read data stage packet"); - omap1510_write_noniso_tx_fifo (endpoint); - /* enable the EP0 tx FIFO to start transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } - } - } else if (status & UDC_STALL) { - UDCDBG ("EP0 stall during TX"); - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } else { - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } -} - -/* Handle RX transaction on non-ISO endpoint. - * This function implements TRM Figure 14-27. - * The ep argument is a physical endpoint number for a non-ISO OUT endpoint - * in the range 1 to 15. - */ -static void omap1510_udc_epn_rx (int ep) -{ - unsigned short status; - - /* Check endpoint status */ - status = inw (UDC_STAT_FLG); - - if (status & UDC_ACK) { - int nbytes; - struct usb_endpoint_instance *endpoint = - omap1510_find_ep (ep); - - nbytes = omap1510_read_noniso_rx_fifo (endpoint); - usbd_rcv_complete (endpoint, nbytes, 0); - - /* enable rx FIFO to prepare for next packet */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - } else if (status & UDC_STALL) { - UDCDBGA ("STALL on RX endpoint %d", ep); - } else if (status & UDC_NAK) { - UDCDBGA ("NAK on RX ep %d", ep); - } else { - serial_printf ("omap-bi: RX on ep %d with status %x", ep, - status); - } -} - -/* Handle TX transaction on non-ISO endpoint. - * This function implements TRM Figure 14-29. - * The ep argument is a physical endpoint number for a non-ISO IN endpoint - * in the range 16 to 30. - */ -static void omap1510_udc_epn_tx (int ep) -{ - unsigned short status; - - /*serial_printf("omap1510_udc_epn_tx( %x )\n",ep); */ - - /* Check endpoint status */ - status = inw (UDC_STAT_FLG); - - if (status & UDC_ACK) { - struct usb_endpoint_instance *endpoint = - omap1510_find_ep (ep); - - /* We need to transmit a terminating zero-length packet now if - * we have sent all of the data in this URB and the transfer - * size was an exact multiple of the packet size. - */ - if (endpoint->tx_urb - && (endpoint->last == endpoint->tx_packetSize) - && (endpoint->tx_urb->actual_length - endpoint->sent - - endpoint->last == 0)) { - /* Prepare to transmit a zero-length packet. */ - endpoint->sent += endpoint->last; - /* write 0 bytes of data to FIFO */ - omap1510_write_noniso_tx_fifo (endpoint); - /* enable tx FIFO to start transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - } else if (endpoint->tx_urb - && endpoint->tx_urb->actual_length) { - /* retire the data that was just sent */ - usbd_tx_complete (endpoint); - /* Check to see if we have more data ready to transmit - * now. - */ - if (endpoint->tx_urb - && endpoint->tx_urb->actual_length) { - /* write data to FIFO */ - omap1510_write_noniso_tx_fifo (endpoint); - /* enable tx FIFO to start transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - } - } - } else if (status & UDC_STALL) { - UDCDBGA ("STALL on TX endpoint %d", ep); - } else if (status & UDC_NAK) { - UDCDBGA ("NAK on TX endpoint %d", ep); - } else { - /*serial_printf("omap-bi: TX on ep %d with status %x\n", ep, status); */ - } -} - - -/* -------------------------------------------------------------------------------- -*/ - -/* Handle general USB interrupts and dispatch according to type. - * This function implements TRM Figure 14-13. - */ -void omap1510_udc_irq (void) -{ - u16 irq_src = inw (UDC_IRQ_SRC); - int valid_irq = 0; - - if (!(irq_src & ~UDC_SOF_Flg)) /* ignore SOF interrupts ) */ - return; - - UDCDBGA ("< IRQ #%d start >- %x", udc_interrupts, irq_src); - /*serial_printf("< IRQ #%d start >- %x\n", udc_interrupts, irq_src); */ - - if (irq_src & UDC_DS_Chg) { - /* Device status changed */ - omap1510_udc_state_changed (); - valid_irq++; - } - if (irq_src & UDC_EP0_RX) { - /* Endpoint 0 receive */ - outw (UDC_EP0_RX, UDC_IRQ_SRC); /* ack interrupt */ - omap1510_udc_ep0_rx (udc_device->bus->endpoint_array + 0); - valid_irq++; - } - if (irq_src & UDC_EP0_TX) { - /* Endpoint 0 transmit */ - outw (UDC_EP0_TX, UDC_IRQ_SRC); /* ack interrupt */ - omap1510_udc_ep0_tx (udc_device->bus->endpoint_array + 0); - valid_irq++; - } - if (irq_src & UDC_Setup) { - /* Device setup */ - omap1510_udc_setup (udc_device->bus->endpoint_array + 0); - valid_irq++; - } - /*if (!valid_irq) */ - /* serial_printf("unknown interrupt, IRQ_SRC %.4x\n", irq_src); */ - UDCDBGA ("< IRQ #%d end >", udc_interrupts); - udc_interrupts++; -} - -/* This function implements TRM Figure 14-26. */ -void omap1510_udc_noniso_irq (void) -{ - unsigned short epnum; - unsigned short irq_src = inw (UDC_IRQ_SRC); - int valid_irq = 0; - - if (!(irq_src & (UDC_EPn_RX | UDC_EPn_TX))) - return; - - UDCDBGA ("non-ISO IRQ, IRQ_SRC %x", inw (UDC_IRQ_SRC)); - - if (irq_src & UDC_EPn_RX) { /* Endpoint N OUT transaction */ - /* Determine the endpoint number for this interrupt */ - epnum = (inw (UDC_EPN_STAT) & 0x0f00) >> 8; - UDCDBGA ("RX on ep %x", epnum); - - /* acknowledge interrupt */ - outw (UDC_EPn_RX, UDC_IRQ_SRC); - - if (epnum) { - /* select the endpoint FIFO */ - outw (UDC_EP_Sel | epnum, UDC_EP_NUM); - - omap1510_udc_epn_rx (epnum); - - /* deselect the endpoint FIFO */ - outw (epnum, UDC_EP_NUM); - } - valid_irq++; - } - if (irq_src & UDC_EPn_TX) { /* Endpoint N IN transaction */ - /* Determine the endpoint number for this interrupt */ - epnum = (inw (UDC_EPN_STAT) & 0x000f) | USB_DIR_IN; - UDCDBGA ("TX on ep %x", epnum); - - /* acknowledge interrupt */ - outw (UDC_EPn_TX, UDC_IRQ_SRC); - - if (epnum) { - /* select the endpoint FIFO */ - outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM); - - omap1510_udc_epn_tx (epnum); - - /* deselect the endpoint FIFO */ - outw (UDC_EP_Dir | epnum, UDC_EP_NUM); - } - valid_irq++; - } - if (!valid_irq) - serial_printf (": unknown non-ISO interrupt, IRQ_SRC %.4x\n", - irq_src); -} - -/* -------------------------------------------------------------------------------- -*/ - - -/* - * Start of public functions. - */ - -/* Called to start packet transmission. */ -int udc_endpoint_write (struct usb_endpoint_instance *endpoint) -{ - unsigned short epnum = - endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; - - UDCDBGA ("Starting transmit on ep %x", epnum); - - if (endpoint->tx_urb) { - /* select the endpoint FIFO */ - outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM); - /* write data to FIFO */ - omap1510_write_noniso_tx_fifo (endpoint); - /* enable tx FIFO to start transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect the endpoint FIFO */ - outw (UDC_EP_Dir | epnum, UDC_EP_NUM); - } - - return 0; -} - -/* Start to initialize h/w stuff */ -int udc_init (void) -{ - u16 udc_rev; - uchar value; - ulong gpio; - int i; - - /* Let the device settle down before we start */ - for (i = 0; i < UDC_INIT_MDELAY; i++) udelay(1000); - - udc_device = NULL; - - UDCDBG ("starting"); - - /* Check peripheral reset. Must be 1 to make sure - MPU TIPB peripheral reset is inactive */ - UDCREG (ARM_RSTCT2); - - /* Set and check clock control. - * We might ought to be using the clock control API to do - * this instead of fiddling with the clock registers directly - * here. - */ - outw ((1 << 4) | (1 << 5), CLOCK_CTRL); - UDCREG (CLOCK_CTRL); - - /* Set and check SOFT - * The below line of code has been changed to perform a - * read-modify-write instead of a simple write for - * configuring the SOFT_REQ register. This allows the code - * to be compatible with OMAP5912 and OMAP16xx devices - */ - outw ((1 << 4) | (1 << 3) | 1 | (inw(SOFT_REQ)), SOFT_REQ); - - /* Short delay to wait for DPLL */ - udelay (1000); - - /* Print banner with device revision */ - udc_rev = inw (UDC_REV) & 0xff; - -#ifdef CONFIG_OMAP1610 - printf ("USB: TI OMAP5912 USB function module rev %d.%d\n", - udc_rev >> 4, udc_rev & 0xf); -#endif - - /* The VBUS_MODE bit selects whether VBUS detection is done via - * software (1) or hardware (0). When software detection is - * selected, VBUS_CTRL selects whether USB is not connected (0) - * or connected (1). - */ - outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0); - outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0); - UDCREGL (FUNC_MUX_CTRL_0); - - /* - * At this point, device is ready for configuration... - */ - - UDCDBG ("disable USB interrupts"); - outw (0, UDC_IRQ_EN); - UDCREG (UDC_IRQ_EN); - - UDCDBG ("disable USB DMA"); - outw (0, UDC_DMA_IRQ_EN); - UDCREG (UDC_DMA_IRQ_EN); - - UDCDBG ("initialize SYSCON1"); - outw (UDC_Self_Pwr | UDC_Pullup_En, UDC_SYSCON1); - UDCREG (UDC_SYSCON1); - - return 0; -} - -/* Stall endpoint */ -static void udc_stall_ep (unsigned int ep_addr) -{ - /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - - UDCDBGA ("stall ep_addr %d", ep_addr); - - /* REVISIT? - * The OMAP TRM section 14.2.4.2 says we must check that the FIFO - * is empty before halting the endpoint. The current implementation - * doesn't check that the FIFO is empty. - */ - - if (!ep_num) { - outw (UDC_Stall_Cmd, UDC_SYSCON2); - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) { - if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) { - /* we have a valid rx endpoint, so halt it */ - outw (UDC_EP_Sel | ep_num, UDC_EP_NUM); - outw (UDC_Set_Halt, UDC_CTRL); - outw (ep_num, UDC_EP_NUM); - } - } else { - if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) { - /* we have a valid tx endpoint, so halt it */ - outw (UDC_EP_Sel | UDC_EP_Dir | ep_num, UDC_EP_NUM); - outw (UDC_Set_Halt, UDC_CTRL); - outw (ep_num, UDC_EP_NUM); - } - } -} - -/* Reset endpoint */ -#if 0 -static void udc_reset_ep (unsigned int ep_addr) -{ - /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - - UDCDBGA ("reset ep_addr %d", ep_addr); - - if (!ep_num) { - /* control endpoint 0 can't be reset */ - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) { - UDCDBGA ("UDC_EP_RX(%d) = 0x%04x", ep_num, - inw (UDC_EP_RX (ep_num))); - if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) { - /* we have a valid rx endpoint, so reset it */ - outw (ep_num | UDC_EP_Sel, UDC_EP_NUM); - outw (UDC_Reset_EP, UDC_CTRL); - outw (ep_num, UDC_EP_NUM); - UDCDBGA ("OUT endpoint %d reset", ep_num); - } - } else { - UDCDBGA ("UDC_EP_TX(%d) = 0x%04x", ep_num, - inw (UDC_EP_TX (ep_num))); - /* Resetting of tx endpoints seems to be causing the USB function - * module to fail, which causes problems when the driver is - * uninstalled. We'll skip resetting tx endpoints for now until - * we figure out what the problem is. - */ -#if 0 - if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) { - /* we have a valid tx endpoint, so reset it */ - outw (ep_num | UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); - outw (UDC_Reset_EP, UDC_CTRL); - outw (ep_num | UDC_EP_Dir, UDC_EP_NUM); - UDCDBGA ("IN endpoint %d reset", ep_num); - } -#endif - } -} -#endif - -/* ************************************************************************** */ - -/** - * udc_check_ep - check logical endpoint - * - * Return physical endpoint number to use for this logical endpoint or zero if not valid. - */ -#if 0 -int udc_check_ep (int logical_endpoint, int packetsize) -{ - if ((logical_endpoint == 0x80) || - ((logical_endpoint & 0x8f) != logical_endpoint)) { - return 0; - } - - switch (packetsize) { - case 8: - case 16: - case 32: - case 64: - case 128: - case 256: - case 512: - break; - default: - return 0; - } - - return EP_ADDR_TO_PHYS_EP (logical_endpoint); -} -#endif - -/* - * udc_setup_ep - setup endpoint - * - * Associate a physical endpoint with endpoint_instance - */ -void udc_setup_ep (struct usb_device_instance *device, - unsigned int ep, struct usb_endpoint_instance *endpoint) -{ - UDCDBGA ("setting up endpoint addr %x", endpoint->endpoint_address); - - /* This routine gets called by bi_modinit for endpoint 0 and from - * bi_config for all of the other endpoints. bi_config gets called - * during the DEVICE_CREATE, DEVICE_CONFIGURED, and - * DEVICE_SET_INTERFACE events. We need to reconfigure the OMAP packet - * RAM after bi_config scans the selected device configuration and - * initializes the endpoint structures, but before this routine enables - * the OUT endpoint FIFOs. Since bi_config calls this routine in a - * loop for endpoints 1 through UDC_MAX_ENDPOINTS, we reconfigure our - * packet RAM here when ep==1. - * I really hate to do this here, but it seems like the API exported - * by the USB bus interface controller driver to the usbd-bi module - * isn't quite right so there is no good place to do this. - */ - if (ep == 1) { - omap1510_deconfigure_device (); - omap1510_configure_device (device); - } - - if (endpoint && (ep < UDC_MAX_ENDPOINTS)) { - int ep_addr = endpoint->endpoint_address; - - if (!ep_addr) { - /* nothing to do for endpoint 0 */ - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - /* nothing to do for IN (tx) endpoints */ - } else { /* OUT (rx) endpoint */ - if (endpoint->rcv_packetSize) { - /*struct urb* urb = &(urb_out_array[ep&0xFF]); */ - /*urb->endpoint = endpoint; */ - /*urb->device = device; */ - /*urb->buffer_length = sizeof(urb->buffer); */ - - /*endpoint->rcv_urb = urb; */ - omap1510_prepare_endpoint_for_rx (ep_addr); - } - } - } -} - -/** - * udc_disable_ep - disable endpoint - * @ep: - * - * Disable specified endpoint - */ -#if 0 -void udc_disable_ep (unsigned int ep_addr) -{ - /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - struct usb_endpoint_instance *endpoint = omap1510_find_ep (ep_addr); /*udc_device->bus->endpoint_array + ep; */ - - UDCDBGA ("disable ep_addr %d", ep_addr); - - if (!ep_num) { - /* nothing to do for endpoint 0 */ ; - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - if (endpoint->tx_packetSize) { - /* we have a valid tx endpoint */ - /*usbd_flush_tx(endpoint); */ - endpoint->tx_urb = NULL; - } - } else { - if (endpoint->rcv_packetSize) { - /* we have a valid rx endpoint */ - /*usbd_flush_rcv(endpoint); */ - endpoint->rcv_urb = NULL; - } - } -} -#endif - -/* ************************************************************************** */ - -/** - * udc_connected - is the USB cable connected - * - * Return non-zero if cable is connected. - */ -#if 0 -int udc_connected (void) -{ - return ((inw (UDC_DEVSTAT) & UDC_ATT) == UDC_ATT); -} -#endif - -/* Turn on the USB connection by enabling the pullup resistor */ -void udc_connect (void) -{ - UDCDBG ("connect, enable Pullup"); - outl (0x00000018, FUNC_MUX_CTRL_D); -} - -/* Turn off the USB connection by disabling the pullup resistor */ -void udc_disconnect (void) -{ - UDCDBG ("disconnect, disable Pullup"); - outl (0x00000000, FUNC_MUX_CTRL_D); -} - -/* ************************************************************************** */ - - -/* - * udc_disable_interrupts - disable interrupts - * switch off interrupts - */ -#if 0 -void udc_disable_interrupts (struct usb_device_instance *device) -{ - UDCDBG ("disabling all interrupts"); - outw (0, UDC_IRQ_EN); -} -#endif - -/* ************************************************************************** */ - -/** - * udc_ep0_packetsize - return ep0 packetsize - */ -#if 0 -int udc_ep0_packetsize (void) -{ - return EP0_PACKETSIZE; -} -#endif - -/* Switch on the UDC */ -void udc_enable (struct usb_device_instance *device) -{ - UDCDBGA ("enable device %p, status %d", device, device->status); - - /* initialize driver state variables */ - udc_devstat = 0; - - /* Save the device structure pointer */ - udc_device = device; - - /* Setup ep0 urb */ - if (!ep0_urb) { - ep0_urb = - usbd_alloc_urb (udc_device, - udc_device->bus->endpoint_array); - } else { - serial_printf ("udc_enable: ep0_urb already allocated %p\n", - ep0_urb); - } - - UDCDBG ("Check clock status"); - UDCREG (STATUS_REQ); - - /* The VBUS_MODE bit selects whether VBUS detection is done via - * software (1) or hardware (0). When software detection is - * selected, VBUS_CTRL selects whether USB is not connected (0) - * or connected (1). - */ - outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_CTRL | UDC_VBUS_MODE, - FUNC_MUX_CTRL_0); - UDCREGL (FUNC_MUX_CTRL_0); - - omap1510_configure_device (device); -} - -/* Switch off the UDC */ -void udc_disable (void) -{ - UDCDBG ("disable UDC"); - - omap1510_deconfigure_device (); - - /* The VBUS_MODE bit selects whether VBUS detection is done via - * software (1) or hardware (0). When software detection is - * selected, VBUS_CTRL selects whether USB is not connected (0) - * or connected (1). - */ - outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0); - outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0); - UDCREGL (FUNC_MUX_CTRL_0); - - /* Free ep0 URB */ - if (ep0_urb) { - /*usbd_dealloc_urb(ep0_urb); */ - ep0_urb = NULL; - } - - /* Reset device pointer. - * We ought to do this here to balance the initialization of udc_device - * in udc_enable, but some of our other exported functions get called - * by the bus interface driver after udc_disable, so we have to hang on - * to the device pointer to avoid a null pointer dereference. */ - /* udc_device = NULL; */ -} - -/** - * udc_startup - allow udc code to do any additional startup - */ -void udc_startup_events (struct usb_device_instance *device) -{ - /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ - usbd_device_event_irq (device, DEVICE_INIT, 0); - - /* The DEVICE_CREATE event puts the USB device in the state - * STATE_ATTACHED. - */ - usbd_device_event_irq (device, DEVICE_CREATE, 0); - - /* Some USB controller driver implementations signal - * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. - * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED, - * and DEVICE_RESET causes a transition to the state STATE_DEFAULT. - * The OMAP USB client controller has the capability to detect when the - * USB cable is connected to a powered USB bus via the ATT bit in the - * DEVSTAT register, so we will defer the DEVICE_HUB_CONFIGURED and - * DEVICE_RESET events until later. - */ - - udc_enable (device); -} - -/** - * udc_irq - do pseudo interrupts - */ -void udc_irq(void) -{ - /* Loop while we have interrupts. - * If we don't do this, the input chain - * polling delay is likely to miss - * host requests. - */ - while (inw (UDC_IRQ_SRC) & ~UDC_SOF_Flg) { - /* Handle any new IRQs */ - omap1510_udc_irq (); - omap1510_udc_noniso_irq (); - } -} - -/* Flow control */ -void udc_set_nak(int epid) -{ - /* TODO: implement this functionality in omap1510 */ -} - -void udc_unset_nak (int epid) -{ - /* TODO: implement this functionality in omap1510 */ -} diff --git a/include/configs/omap1510.h b/include/configs/omap1510.h deleted file mode 100644 index 5482722..0000000 --- a/include/configs/omap1510.h +++ /dev/null @@ -1,756 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * OMAP hardware map - * - * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) - * Author: RidgeRun, Inc. - * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/sizes.h> - -/* - There are 2 sets of general I/O --> - 1. GPIO (shared between ARM & DSP, configured by ARM) - 2. MPUIO which can be used only by the ARM. - - Base address FFFB:5000 is where the ARM accesses the MPUIO control registers - (see 7.2.2 of the TRM for MPUIO reg definitions). - - Base address E101:5000 is reserved for ARM access of the same MPUIO control - regs, but via the DSP I/O map. This address is unavailable on 1510. - - Base address FFFC:E000 is where the ARM accesses the GPIO config registers - directly via its own peripheral bus. - - Base address E101:E000 is where the ARM can access the same GPIO config - registers, but the access takes place through the ARM port interface (called - API or MPUI) via the DSP's peripheral bus (DSP I/O space). - - Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses - instead of the E101:E000 addresses. The DSP has only read access of the pin - control register, so this may explain the inability to write to E101:E018. - Try accessing pin control reg at FFFC:E018. - */ -#define OMAP1510_GPIO_BASE 0xfffce000 -#define OMAP1510_GPIO_START OMAP1510_GPIO_BASE -#define OMAP1510_GPIO_SIZE SZ_4K - -#define OMAP1510_MCBSP1_BASE 0xE1011000 -#define OMAP1510_MCBSP1_SIZE SZ_4K -#define OMAP1510_MCBSP1_START 0xE1011000 - -#define OMAP1510_MCBSP2_BASE 0xFFFB1000 - -#define OMAP1510_MCBSP3_BASE 0xE1017000 -#define OMAP1510_MCBSP3_SIZE SZ_4K -#define OMAP1510_MCBSP3_START 0xE1017000 - -/* - * Where's the flush address (for flushing D and I cache?) - */ -#define FLUSH_BASE 0xdf000000 -#define FLUSH_BASE_PHYS 0x00000000 - -#ifndef __ASSEMBLER__ - -#define PCIO_BASE 0 - -/* - * RAM definitions - */ -#define MAPTOPHYS(a) ((unsigned long)(a) - PAGE_OFFSET) -#define KERNTOPHYS(a) ((unsigned long)(&a)) -#define KERNEL_BASE (0x10008000) -#endif - -/* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) ((x)) - -/* ---------------------------------------------------------------------------- - * OMAP1510 system registers - * ---------------------------------------------------------------------------- - */ - -#define OMAP1510_UART1_BASE 0xfffb0000 /* "BLUETOOTH-UART" */ -#define OMAP1510_UART2_BASE 0xfffb0800 /* "MODEM-UART" */ -#define OMAP1510_RTC_BASE 0xfffb4800 /* RTC */ -#define OMAP1510_UART3_BASE 0xfffb9800 /* Shared MPU/DSP UART */ -#define OMAP1510_COM_MCBSP2_BASE 0xffff1000 /* Com McBSP2 */ -#define OMAP1510_AUDIO_MCBSP_BASE 0xffff1800 /* Audio McBSP2 */ -#define OMAP1510_ARMIO_BASE 0xfffb5000 /* keyboard/gpio */ - -/* - * OMAP1510 UART3 Registers - */ - -#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */ - -/* UART3 Registers Maping through MPU bus */ - -#define UART3_RHR (OMAP_MPU_UART3_BASE + 0) -#define UART3_THR (OMAP_MPU_UART3_BASE + 0) -#define UART3_DLL (OMAP_MPU_UART3_BASE + 0) -#define UART3_IER (OMAP_MPU_UART3_BASE + 4) -#define UART3_DLH (OMAP_MPU_UART3_BASE + 4) -#define UART3_IIR (OMAP_MPU_UART3_BASE + 8) -#define UART3_FCR (OMAP_MPU_UART3_BASE + 8) -#define UART3_EFR (OMAP_MPU_UART3_BASE + 8) -#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C) -#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10) -#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10) -#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14) -#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14) -#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20) -#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24) -#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28) -#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28) -#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C) -#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C) -#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30) -#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30) -#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34) -#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34) -#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38) -#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C) -#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C) -#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40) -#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44) -#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48) -#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C) -#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50) - -/* - * Configuration Registers - */ -#define FUNC_MUX_CTRL_0 0xfffe1000 -#define FUNC_MUX_CTRL_1 0xfffe1004 -#define FUNC_MUX_CTRL_2 0xfffe1008 -#define COMP_MODE_CTRL_0 0xfffe100c -#define FUNC_MUX_CTRL_3 0xfffe1010 -#define FUNC_MUX_CTRL_4 0xfffe1014 -#define FUNC_MUX_CTRL_5 0xfffe1018 -#define FUNC_MUX_CTRL_6 0xfffe101C -#define FUNC_MUX_CTRL_7 0xfffe1020 -#define FUNC_MUX_CTRL_8 0xfffe1024 -#define FUNC_MUX_CTRL_9 0xfffe1028 -#define FUNC_MUX_CTRL_A 0xfffe102C -#define FUNC_MUX_CTRL_B 0xfffe1030 -#define FUNC_MUX_CTRL_C 0xfffe1034 -#define FUNC_MUX_CTRL_D 0xfffe1038 -#define PULL_DWN_CTRL_0 0xfffe1040 -#define PULL_DWN_CTRL_1 0xfffe1044 -#define PULL_DWN_CTRL_2 0xfffe1048 -#define PULL_DWN_CTRL_3 0xfffe104c -#define GATE_INH_CTRL_0 0xfffe1050 -#define VOLTAGE_CTRL_0 0xfffe1060 -#define TEST_DBG_CTRL_0 0xfffe1070 - -#define MOD_CONF_CTRL_0 0xfffe1080 - -#ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */ - -#define USB_OTG_CTRL 0xFFFB040C -#define USB_TRANSCEIVER_CTRL 0xFFFE1064 -#define PULL_DWN_CTRL_4 0xFFFE10AC -#define PU_PD_SEL_0 0xFFFE10B4 -#define PU_PD_SEL_1 0xFFFE10B8 -#define PU_PD_SEL_2 0xFFFE10BC -#define PU_PD_SEL_3 0xFFFE10C0 -#define PU_PD_SEL_4 0xFFFE10C4 - -#endif -/* - * Traffic Controller Memory Interface Registers - */ -#define TCMIF_BASE 0xfffecc00 -#define IMIF_PRIO (TCMIF_BASE + 0x00) -#define EMIFS_PRIO_REG (TCMIF_BASE + 0x04) -#define EMIFF_PRIO_REG (TCMIF_BASE + 0x08) -#define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c) -#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) -#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) -#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) -#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) -#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) -#define EMIFF_MRS (TCMIF_BASE + 0x24) -#define TC_TIMEOUT1 (TCMIF_BASE + 0x28) -#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) -#define TC_TIMEOUT3 (TCMIF_BASE + 0x30) -#define TC_ENDIANISM (TCMIF_BASE + 0x34) -#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) -#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) - -/* - * LCD Panel - */ -#define TI925_LCD_BASE 0xFFFEC000 -#define TI925_LCD_CONTROL (TI925_LCD_BASE) -#define TI925_LCD_TIMING0 (TI925_LCD_BASE+0x4) -#define TI925_LCD_TIMING1 (TI925_LCD_BASE+0x8) -#define TI925_LCD_TIMING2 (TI925_LCD_BASE+0xc) -#define TI925_LCD_STATUS (TI925_LCD_BASE+0x10) -#define TI925_LCD_SUBPANEL (TI925_LCD_BASE+0x14) - -#define OMAP_LCD_CONTROL TI925_LCD_CONTROL - -/* I2C Registers */ - -#define I2C_BASE 0xfffb3800 - -#define I2C_REV (I2C_BASE + 0x00) -#define I2C_IE (I2C_BASE + 0x04) -#define I2C_STAT (I2C_BASE + 0x08) -#define I2C_IV (I2C_BASE + 0x0c) -#define I2C_BUF (I2C_BASE + 0x14) -#define I2C_CNT (I2C_BASE + 0x18) -#define I2C_DATA (I2C_BASE + 0x1c) -#define I2C_CON (I2C_BASE + 0x24) -#define I2C_OA (I2C_BASE + 0x28) -#define I2C_SA (I2C_BASE + 0x2c) -#define I2C_PSC (I2C_BASE + 0x30) -#define I2C_SCLL (I2C_BASE + 0x34) -#define I2C_SCLH (I2C_BASE + 0x38) -#define I2C_SYSTEST (I2C_BASE + 0x3c) - -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ - -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_AD0 (1 << 8) /* Address zero */ -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Interrupt Vector Register (I2C_IV): */ - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ - -/* I2C Buffer Configuration Register (I2C_BUF): */ - -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_RM (1 << 2) /* Repeat mode (master mode only) */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C System Test Register (I2C_SYSTEST): */ - -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ - -/* - * MMC/SD Host Controller Registers - */ - -#define OMAP_MMC_CMD 0xFFFB7800 /* MMC Command */ -#define OMAP_MMC_ARGL 0xFFFB7804 /* MMC argument low */ -#define OMAP_MMC_ARGH 0xFFFB7808 /* MMC argument high */ -#define OMAP_MMC_CON 0xFFFB780C /* MMC system configuration */ -#define OMAP_MMC_STAT 0xFFFB7810 /* MMC status */ -#define OMAP_MMC_IE 0xFFFB7814 /* MMC system interrupt enable */ -#define OMAP_MMC_CTO 0xFFFB7818 /* MMC command time-out */ -#define OMAP_MMC_DTO 0xFFFB781C /* MMC data time-out */ -#define OMAP_MMC_DATA 0xFFFB7820 /* MMC TX/RX FIFO data */ -#define OMAP_MMC_BLEN 0xFFFB7824 /* MMC block length */ -#define OMAP_MMC_NBLK 0xFFFB7828 /* MMC number of blocks */ -#define OMAP_MMC_BUF 0xFFFB782C /* MMC buffer configuration */ -#define OMAP_MMC_SPI 0xFFFB7830 /* MMC serial port interface */ -#define OMAP_MMC_SDIO 0xFFFB7834 /* MMC SDIO mode configuration */ -#define OMAP_MMC_SYST 0xFFFB7838 /* MMC system test */ -#define OMAP_MMC_REV 0xFFFB783C /* MMC module version */ -#define OMAP_MMC_RSP0 0xFFFB7840 /* MMC command response 0 */ -#define OMAP_MMC_RSP1 0xFFFB7844 /* MMC command response 1 */ -#define OMAP_MMC_RSP2 0xFFFB7848 /* MMC command response 2 */ -#define OMAP_MMC_RSP3 0xFFFB784C /* MMC command response 3 */ -#define OMAP_MMC_RSP4 0xFFFB7850 /* MMC command response 4 */ -#define OMAP_MMC_RSP5 0xFFFB7854 /* MMC command response 5 */ -#define OMAP_MMC_RSP6 0xFFFB7858 /* MMC command response 6 */ -#define OMAP_MMC_RSP7 0xFFFB785C /* MMC command response 4 */ - -/* MMC masks */ - -#define OMAP_MMC_END_OF_CMD (1 << 0) /* End of command phase */ -#define OMAP_MMC_CARD_BUSY (1 << 2) /* Card enter busy state */ -#define OMAP_MMC_BLOCK_RS (1 << 3) /* Block received/sent */ -#define OMAP_MMC_EOF_BUSY (1 << 4) /* Card exit busy state */ -#define OMAP_MMC_DATA_TIMEOUT (1 << 5) /* Data response time-out */ -#define OMAP_MMC_DATA_CRC (1 << 6) /* Date CRC error */ -#define OMAP_MMC_CMD_TIMEOUT (1 << 7) /* Command response time-out */ -#define OMAP_MMC_CMD_CRC (1 << 8) /* Command CRC error */ -#define OMAP_MMC_A_FULL (1 << 10) /* Buffer almost full */ -#define OMAP_MMC_A_EMPTY (1 << 11) /* Buffer almost empty */ -#define OMAP_MMC_OCR_BUSY (1 << 12) /* OCR busy */ -#define OMAP_MMC_CARD_IRQ (1 << 13) /* Card IRQ received */ -#define OMAP_MMC_CARD_ERR (1 << 14) /* Card status error in response */ - -/* 2.9.2 MPUI Interface Registers FFFE:C900 */ - -#define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900) -#define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904) -#define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908) -#define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c) -#define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910) -#define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914) -#define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918) -#define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c) - -/* 2.9.6 Traffic Controller Memory Interface Registers: */ -#define OMAP_IMIF_PRIO_REG 0xfffecc00 -#define OMAP_EMIFS_PRIO_REG 0xfffecc04 -#define OMAP_EMIFF_PRIO_REG 0xfffecc08 -#define OMAP_EMIFS_CONFIG_REG 0xfffecc0c -#define OMAP_EMIFS_CS0_CONFIG 0xfffecc10 -#define OMAP_EMIFS_CS1_CONFIG 0xfffecc14 -#define OMAP_EMIFS_CS2_CONFIG 0xfffecc18 -#define OMAP_EMIFS_CS3_CONFIG 0xfffecc1c -#define OMAP_EMIFF_SDRAM_CONFIG 0xfffecc20 -#define OMAP_EMIFF_MRS 0xfffecc24 -#define OMAP_TIMEOUT1 0xfffecc28 -#define OMAP_TIMEOUT2 0xfffecc2c -#define OMAP_TIMEOUT3 0xfffecc30 -#define OMAP_ENDIANISM 0xfffecc34 - -/* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */ -#define OMAP_EMIFS_CONFIG_FR (1 << 4) -#define OMAP_EMIFS_CONFIG_PDE (1 << 3) -#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) -#define OMAP_EMIFS_CONFIG_BM (1 << 1) -#define OMAP_EMIFS_CONFIG_WP (1 << 0) - -/* - * Memory chunk set aside for the Framebuffer in SRAM - */ -#define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE - - -/* - * DMA - */ - -#define OMAP1510_DMA_BASE 0xFFFED800 -#define OMAP_DMA_BASE OMAP1510_DMA_BASE - -/* Global Register selection */ -#define NO_GLOBAL_DMA_ACCESS 0 - -/* Channel select field - * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc... - */ -#define LCD_CHANNEL 0xc - -/* Register Select Field (LCD) */ -#define DMA_LCD_CTRL 0 -#define DMA_LCD_TOP_F1_L 1 -#define DMA_LCD_TOP_F1_U 2 -#define DMA_LCD_BOT_F1_L 3 -#define DMA_LCD_BOT_F1_U 4 - -#define LCD_FRAME_MODE (1<<0) -#define LCD_FRAME_IT_IE (1<<1) -#define LCD_BUS_ERROR_IT_IE (1<<2) -#define LCD_FRAME_1_IT_COND (1<<3) -#define LCD_FRAME_2_IT_COND (1<<4) -#define LCD_BUS_ERROR_IT_COND (1<<5) -#define LCD_SOURCE_IMIF (1<<6) - -/* - * Real-Time Clock - */ - -#define RTC_SECONDS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00) -#define RTC_MINUTES (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04) -#define RTC_HOURS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08) -#define RTC_DAYS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C) -#define RTC_MONTHS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10) -#define RTC_YEARS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14) -#define RTC_CTRL (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40) - - -/* --------------------------------------------------------------------------- - * OMAP1510 Interrupt Handlers - * --------------------------------------------------------------------------- - * - */ -#define OMAP_IH1_BASE 0xfffecb00 -#define OMAP_IH2_BASE 0xfffe0000 -#define OMAP1510_ITR 0x0 -#define OMAP1510_MASK 0x4 - -#define INTERRUPT_HANDLER_BASE OMAP_IH1_BASE -#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR -#define INTERRUPT_MASK_REGISTER OMAP1510_MASK - - -/* --------------------------------------------------------------------------- - * OMAP1510 TIMERS - * --------------------------------------------------------------------------- - * - */ - -#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000 - -/* 32k Timer Registers */ -#define TIMER32k_CR 0x08 -#define TIMER32k_TVR 0x00 -#define TIMER32k_TCR 0x04 - -/* 32k Timer Control Register definition */ -#define TIMER32k_TSS (1<<0) -#define TIMER32k_TRB (1<<1) -#define TIMER32k_INT (1<<2) -#define TIMER32k_ARL (1<<3) - -/* MPU Timer base addresses */ -#define OMAP1510_MPUTIMER_BASE 0xfffec500 -#define OMAP1510_MPUTIMER_OFF 0x00000100 - -#define OMAP1510_TIMER1_BASE 0xfffec500 -#define OMAP1510_TIMER2_BASE 0xfffec600 -#define OMAP1510_TIMER3_BASE 0xfffec700 - -/* MPU Timer Registers */ -#define CNTL_TIMER 0 -#define LOAD_TIM 4 -#define READ_TIM 8 - -/* CNTL_TIMER register bits */ -#define MPUTIM_FREE (1<<6) -#define MPUTIM_CLOCK_ENABLE (1<<5) -#define MPUTIM_PTV_MASK (0x7<<MPUTIM_PTV_BIT) -#define MPUTIM_PTV_BIT 2 -#define MPUTIM_AR (1<<1) -#define MPUTIM_ST (1<<0) - -/* --------------------------------------------------------------------------- - * OMAP1510 GPIO (SHARED) - * --------------------------------------------------------------------------- - * - */ -#define GPIO_DATA_INPUT_REG (OMAP1510_GPIO_BASE + 0x0) -#define GPIO_DATA_OUTPUT_REG (OMAP1510_GPIO_BASE + 0x4) -#define GPIO_DIR_CONTROL_REG (OMAP1510_GPIO_BASE + 0x8) -#define GPIO_INT_CONTROL_REG (OMAP1510_GPIO_BASE + 0xc) -#define GPIO_INT_MASK_REG (OMAP1510_GPIO_BASE + 0x10) -#define GPIO_INT_STATUS_REG (OMAP1510_GPIO_BASE + 0x14) -#define GPIO_PIN_CONTROL_REG (OMAP1510_GPIO_BASE + 0x18) - - -/* --------------------------- - * OMAP1510 MPUIO (ARM only) - *---------------------------- - */ -#define OMAP1510_MPUIO_BASE 0xFFFB5000 -#define MPUIO_DATA_INPUT_REG (OMAP1510_MPUIO_BASE + 0x0) -#define MPUIO_DATA_OUTPUT_REG (OMAP1510_MPUIO_BASE + 0x4) -#define MPUIO_DIR_CONTROL_REG (OMAP1510_MPUIO_BASE + 0x8) - -/* --------------------------------------------------------------------------- - * OMAP1510 TIPB (only) - * --------------------------------------------------------------------------- - * - */ -#define TIPB_PUBLIC_CNTL_BASE 0xfffed300 -#define MPU_PUBLIC_TIPB_CNTL_REG (TIPB_PUBLIC_CNTL_BASE + 0x8) -#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 -#define MPU_PRIVATE_TIPB_CNTL_REG (TIPB_PRIVATE_CNTL_BASE + 0x8) - -/* - * --------------------------------------------------------------------------- - * OMAP1510 Camera Interface - * --------------------------------------------------------------------------- - */ -#define CAMERA_BASE (IO_BASE + 0x6800) -#define CAM_CTRLCLOCK_REG (CAMERA_BASE + 0x00) -#define CAM_IT_STATUS_REG (CAMERA_BASE + 0x04) -#define CAM_MODE_REG (CAMERA_BASE + 0x08) -#define CAM_STATUS_REG (CAMERA_BASE + 0x0C) -#define CAM_CAMDATA_REG (CAMERA_BASE + 0x10) -#define CAM_GPIO_REG (CAMERA_BASE + 0x14) -#define CAM_PEAK_CTR_REG (CAMERA_BASE + 0x18) - -#if 0 -#ifndef __ASSEMBLY__ -typedef struct { - __u32 ctrlclock; - __u32 it_status; - __u32 mode; - __u32 status; - __u32 camdata; - __u32 gpio; - __u32 peak_counter; -} camera_regs_t; -#endif -#endif - -/* CTRLCLOCK bit shifts */ -#define FOSCMOD_BIT 0 -#define FOSCMOD_MASK (0x7 << FOSCMOD_BIT) -#define FOSCMOD_12MHz 0x0 -#define FOSCMOD_6MHz 0x2 -#define FOSCMOD_9_6MHz 0x4 -#define FOSCMOD_24MHz 0x5 -#define FOSCMOD_8MHz 0x6 -#define POLCLK (1<<3) -#define CAMEXCLK_EN (1<<4) -#define MCLK_EN (1<<5) -#define DPLL_EN (1<<6) -#define LCLK_EN (1<<7) - -/* IT_STATUS bit shifts */ -#define V_UP (1<<0) -#define V_DOWN (1<<1) -#define H_UP (1<<2) -#define H_DOWN (1<<3) -#define FIFO_FULL (1<<4) -#define DATA_XFER (1<<5) - -/* MODE bit shifts */ -#define CAMOSC (1<<0) -#define IMGSIZE_BIT 1 -#define IMGSIZE_MASK (0x3 << IMGSIZE_BIT) -#define IMGSIZE_CIF (0x0 << IMGSIZE_BIT) /* 352x288 */ -#define IMGSIZE_QCIF (0x1 << IMGSIZE_BIT) /* 176x144 */ -#define IMGSIZE_VGA (0x2 << IMGSIZE_BIT) /* 640x480 */ -#define IMGSIZE_QVGA (0x3 << IMGSIZE_BIT) /* 320x240 */ -#define ORDERCAMD (1<<3) -#define EN_V_UP (1<<4) -#define EN_V_DOWN (1<<5) -#define EN_H_UP (1<<6) -#define EN_H_DOWN (1<<7) -#define EN_DMA (1<<8) -#define THRESHOLD (1<<9) -#define THRESHOLD_BIT 9 -#define THRESHOLD_MASK (0x7f<<9) -#define EN_NIRQ (1<<16) -#define EN_FIFO_FULL (1<<17) -#define RAZ_FIFO (1<<18) - -/* STATUS bit shifts */ -#define VSTATUS (1<<0) -#define HSTATUS (1<<1) - -/* GPIO bit shifts */ -#define CAM_RST (1<<0) - - -/********************* - * Watchdog timer. - *********************/ -#define WDTIM_BASE 0xfffec800 -#define WDTIM_CONTROL (WDTIM_BASE+0x00) -#define WDTIM_LOAD (WDTIM_BASE+0x04) -#define WDTIM_READ (WDTIM_BASE+0x04) -#define WDTIM_MODE (WDTIM_BASE+0x08) - -/* Values to write to mode register to disable the watchdog function. */ -#define DISABLE_SEQ1 0xF5 -#define DISABLE_SEQ2 0xA0 - -/* WDTIM_CONTROL bit definitions. */ -#define WDTIM_CONTROL_ST BIT7 - - -/* --------------------------------------------------------------------------- - * Differentiating processor versions for those who care. - * --------------------------------------------------------------------------- - * - */ -#define OMAP1509 0 -#define OMAP1510 1 - -#define OMAP1510_ID_CODE_REG 0xfffed404 - -#ifndef __ASSEMBLY__ -int cpu_type(void); -#endif - -/*****************************************************************************/ - -#define CLKGEN_RESET_BASE (0xfffece00) -#define ARM_CKCTL (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0) -#define ARM_IDLECT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4) -#define ARM_IDLECT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8) -#define ARM_EWUPCT (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC) -#define ARM_RSTCT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10) -#define ARM_RSTCT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14) -#define ARM_SYSST (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18) - - -#define CK_CLKIN 12 /* MHz */ -#define CK_RATEF 1 -#define CK_IDLEF 2 -#define CK_ENABLEF 4 -#define CK_SELECTF 8 -#ifndef __ASSEMBLER__ -#define CK_DPLL1 ((volatile __u16 *)0xfffecf00) -#else -#define CK_DPLL1 (0xfffecf00) -#endif -#define SETARM_IDLE_SHIFT - -/* ARM_CKCTL bit shifts */ -#define PERDIV 0 -#define LCDDIV 2 -#define ARMDIV 4 -#define DSPDIV 6 -#define TCDIV 8 -#define DSPMMUDIV 10 -#define ARM_TIMXO 12 -#define EN_DSPCK 13 -#define ARM_INTHCK_SEL 14 /* REVISIT -- where is this used? */ - -#define ARM_CKCTL_RSRVD_BIT15 (1 << 15) -#define ARM_CKCTL_ARM_INTHCK_SEL (1 << 14) -#define ARM_CKCTL_EN_DSPCK (1 << 13) -#define ARM_CKCTL_ARM_TIMXO (1 << 12) -#define ARM_CKCTL_DSPMMU_DIV1 (1 << 11) -#define ARM_CKCTL_DSPMMU_DIV2 (1 << 10) -#define ARM_CKCTL_TCDIV1 (1 << 9) -#define ARM_CKCTL_TCDIV2 (1 << 8) -#define ARM_CKCTL_DSPDIV1 (1 << 7) -#define ARM_CKCTL_DSPDIV0 (1 << 6) -#define ARM_CKCTL_ARMDIV1 (1 << 5) -#define ARM_CKCTL_ARMDIV0 (1 << 4) -#define ARM_CKCTL_LCDDIV1 (1 << 3) -#define ARM_CKCTL_LCDDIV0 (1 << 2) -#define ARM_CKCTL_PERDIV1 (1 << 1) -#define ARM_CKCTL_PERDIV0 (1 << 0) - -/* ARM_IDLECT1 bit shifts */ -#define IDLWDT_ARM 0 -#define IDLXORP_ARM 1 -#define IDLPER_ARM 2 -#define IDLLCD_ARM 3 -#define IDLLB_ARM 4 -#define IDLHSAB_ARM 5 -#define IDLIF_ARM 6 -#define IDLDPLL_ARM 7 -#define IDLAPI_ARM 8 -#define IDLTIM_ARM 9 -#define SETARM_IDLE 11 - -/* ARM_IDLECT2 bit shifts */ -#define EN_WDTCK 0 -#define EN_XORPCK 1 -#define EN_PERCK 2 -#define EN_LCDCK 3 -#define EN_LBCK 4 -#define EN_HSABCK 5 -#define EN_APICK 6 -#define EN_TIMCK 7 -#define DMACK_REQ 8 -#define EN_GPIOCK 9 -#define EN_LBFREECK 10 - -#define ARM_RSTCT1_SW_RST (1 << 3) -#define ARM_RSTCT1_DSP_RST (1 << 2) -#define ARM_RSTCT1_DSP_EN (1 << 1) -#define ARM_RSTCT1_ARM_RST (1 << 0) - -/* ARM_RSTCT2 bit shifts */ -#define EN_PER 0 - -#define ARM_SYSST_RSRVD_BIT15 (1 << 15) -#define ARM_SYSST_RSRVD_BIT14 (1 << 14) -#define ARM_SYSST_CLOCK_SELECT2 (1 << 13) -#define ARM_SYSST_CLOCK_SELECT1 (1 << 12) -#define ARM_SYSST_CLOCK_SELECT0 (1 << 11) -#define ARM_SYSST_RSRVD_BIT10 (1 << 10) -#define ARM_SYSST_RSRVD_BIT9 (1 << 9) -#define ARM_SYSST_RSRVD_BIT8 (1 << 8) -#define ARM_SYSST_RSRVD_BIT7 (1 << 7) -#define ARM_SYSST_IDLE_DSP (1 << 6) -#define ARM_SYSST_POR (1 << 5) -#define ARM_SYSST_EXT_RST (1 << 4) -#define ARM_SYSST_ARM_MCRST (1 << 3) -#define ARM_SYSST_ARM_WDRST (1 << 2) -#define ARM_SYSST_GLOB_SWRST (1 << 1) -#define ARM_SYSST_DSP_WDRST (1 << 0) - -/* Table 15-23. DPLL Control Registers: */ -#define DPLL_CTL_REG (volatile __u16 *)(0xfffecf00) - -/* Table 15-24. Control Register (CTL_REG): */ - -#define DPLL_CTL_REG_IOB (1 << 13) -#define DPLL_CTL_REG_PLL_MULT Fld(5,0) - -/*****************************************************************************/ - -/* OMAP INTERRUPT REGISTERS */ -#define IRQ_ITR 0x00 -#define IRQ_MIR 0x04 -#define IRQ_SIR_IRQ 0x10 -#define IRQ_SIR_FIQ 0x14 -#define IRQ_CONTROL_REG 0x18 -#define IRQ_ISR 0x9c -#define IRQ_ILR0 0x1c - -#define REG_IHL1_MIR (OMAP_IH1_BASE+IRQ_MIR) -#define REG_IHL2_MIR (OMAP_IH2_BASE+IRQ_MIR) - -/* INTERRUPT LEVEL REGISTER BITS */ -#define ILR_PRIORITY_MASK (0x3c) -#define ILR_PRIORITY_SHIFT (2) -#define ILR_LEVEL_TRIGGER (1<<1) -#define ILR_FIQ (1<<0) - -#define IRQ_LEVEL_INT 1 -#define IRQ_EDGE_INT 0 - -/* Macros to access registers */ -#define outb(v,p) *(volatile u8 *) (p) = v -#define outw(v,p) *(volatile u16 *) (p) = v -#define outl(v,p) *(volatile u32 *) (p) = v - -#define inb(p) *(volatile u8 *) (p) -#define inw(p) *(volatile u16 *) (p) -#define inl(p) *(volatile u32 *) (p) diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h deleted file mode 100644 index 376dfdb..0000000 --- a/include/configs/omap5912osk.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta kshitij@ti.com - * Configuation settings for the TI OMAP Innovator board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */ -#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */ - -#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ -#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ - -/* input clock of PLL */ -/* the OMAP5912 OSK has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -/* -*/ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04800300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart - on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP5912 OSK */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - -#include <configs/omap1510.h> - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ - root=/dev/nfs rw nfsroot=157.87.82.48:\ - /home/mwd/myfs/target ip=dhcp" -#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ -#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ -#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ -#define CONFIG_BOOTFILE "uImage" /* file to load */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "OMAP5912 OSK # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by - * DPLL1. This time is further subdivided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ - -#define PHYS_SRAM 0x20000000 - -/*----------------------------------------------------------------------- - * FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* addr of environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) - -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET 0x40000 /* environment starts here */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR PHYS_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE (250 * 1024) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE) - -#endif /* __CONFIG_H */