
16 Sep
2014
16 Sep
'14
8:09 p.m.
On Monday, September 15, 2014 at 10:09:34 PM, Dinh Nguyen wrote:
On 09/15/2014 06:06 AM, Marek Vasut wrote:
[...]
- /* get the L4 SP clock which supplied to UART */
- reg = readl(&clock_manager_base->main_pll.maindiv);
- reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg);
- clock = clock / (reg + 1);
This is not a +1. The l4 mp clock divider is structured like this:
0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8 0x4 = divide by 16
So it should be: clock = clock / (1 << reg);
Fixed, thanks! I also synched the clock code with your codebase for all but the SDRAM auto refresh part.
Best regards, Marek Vasut