Implement wait_dat0 mmc ops callbac, allowing to reduce SPL boot time.
Before (using grabserial): [0.000001 0.000001] U-Boot SPL 2021.04-xxxx [0.028257 0.028257] DDRINFO: start DRAM init [0.028500 0.000243] DDRINFO: DRAM rate 3000MTS [0.304627 0.276127] DDRINFO:ddrphy calibration done [0.305647 0.001020] DDRINFO: ddrmix config done [0.352584 0.046937] SEC0: RNG instantiated [0.374299 0.021715] Normal Boot [0.374675 0.000376] Trying to boot from MMC2 [1.250580 0.875905] NOTICE: BL31: v2.4(release):lf-5.10.72-2.2.0-0-g5782363f9 [1.251985 0.001405] NOTICE: BL31: Built : 08:02:40, Apr 12 2022 [1.522560 0.270575] [1.522734 0.000174] [1.522788 0.000054] U-Boot 2021.04-xxxx
After: [0.000001 0.000001] U-Boot SPL 2021.04-xxxx [0.001614 0.001614] DDRINFO: start DRAM init [0.002377 0.000763] DDRINFO: DRAM rate 3000MTS [0.278494 0.276117] DDRINFO:ddrphy calibration done [0.279266 0.000772] DDRINFO: ddrmix config done [0.338432 0.059166] SEC0: RNG instantiated [0.339051 0.000619] Normal Boot [0.339431 0.000380] Trying to boot from MMC2 [0.412587 0.073156] NOTICE: BL31: v2.4(release):lf-5.15.5-1.0.0-0-g05f788b [0.414191 0.001604] NOTICE: BL31: Built : 10:35:26, Apr 6 2022 [0.700685 0.286494] [0.700793 0.000108] [0.700845 0.000052] U-Boot 2021.04-xxxx
Signed-off-by: Loic Poulain loic.poulain@linaro.org --- drivers/mmc/fsl_esdhc_imx.c | 50 ++++++++++++++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 17 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 02208a5..ec52f93 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1060,6 +1060,30 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) return timeout > 0; }
+static int esdhc_wait_dat0_common(struct fsl_esdhc_priv *priv, int state, + int timeout_us) +{ + struct fsl_esdhc *regs = priv->esdhc_regs; + int ret, err; + u32 tmp; + + /* make sure the card clock keep on */ + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + + ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, + !!(tmp & PRSSTAT_DAT0) == !!state, + timeout_us); + + /* change to default setting, let host control the card clock */ + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + + err = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (err) + pr_warn("card clock not gate off as expect.\n"); + + return ret; +} + static int esdhc_reset(struct fsl_esdhc *regs) { ulong start; @@ -1109,11 +1133,19 @@ static int esdhc_set_ios(struct mmc *mmc) return esdhc_set_ios_common(priv, mmc); }
+static int esdhc_wait_dat0(struct mmc *mmc, int state, int timeout_us) +{ + struct fsl_esdhc_priv *priv = mmc->priv; + + return esdhc_wait_dat0_common(priv, state, timeout_us); +} + static const struct mmc_ops esdhc_ops = { .getcd = esdhc_getcd, .init = esdhc_init, .send_cmd = esdhc_send_cmd, .set_ios = esdhc_set_ios, + .wait_dat0 = esdhc_wait_dat0, }; #endif
@@ -1576,25 +1608,9 @@ static int __maybe_unused fsl_esdhc_set_enhanced_strobe(struct udevice *dev) static int fsl_esdhc_wait_dat0(struct udevice *dev, int state, int timeout_us) { - int ret, err; - u32 tmp; struct fsl_esdhc_priv *priv = dev_get_priv(dev); - struct fsl_esdhc *regs = priv->esdhc_regs;
- /* make sure the card clock keep on */ - esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); - - ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, - !!(tmp & PRSSTAT_DAT0) == !!state, - timeout_us); - - /* change to default setting, let host control the card clock */ - esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); - err = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); - if (err) - dev_warn(dev, "card clock not gate off as expect.\n"); - - return ret; + return esdhc_wait_dat0_common(priv, state, timeout_us); }
static const struct dm_mmc_ops fsl_esdhc_ops = {