The handling of the SPI_CPOL bit inside the SPI driver was wrong. As reported by the manual, the meaning of the SSPOL inside the configuration register is the same as reported by SPI specification (0 if low in idle, 1 is high on idle). The driver inverts this logic.
Because this patch sets the logic as specified, it is required to clear the CPOL bit in the configuration file to adapt to the correct logic.
Signed-off-by: Stefano Babic sbabic@denx.de Signed-off-by: David Jander david.jander@protonic.nl --- drivers/spi/mxc_spi.c | 4 ++-- include/configs/imx31_litekit.h | 4 ++-- include/configs/mx31ads.h | 4 ++-- include/configs/mx31pdk.h | 4 ++-- include/configs/mx51evk.h | 2 +- include/configs/qong.h | 4 ++-- 6 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 802cd2e..c6c8f60 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -215,7 +215,7 @@ static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, if (mode & SPI_CS_HIGH) ss_pol = 1;
- if (!(mode & SPI_CPOL)) + if (mode & SPI_CPOL) sclkpol = 1;
if (mode & SPI_CPHA) @@ -412,7 +412,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
if (mode & SPI_CPHA) ctrl_reg |= MXC_CSPICTRL_PHA; - if (!(mode & SPI_CPOL)) + if (mode & SPI_CPOL) ctrl_reg |= MXC_CSPICTRL_POL; if (mode & SPI_CS_HIGH) ctrl_reg |= MXC_CSPICTRL_SSPOL; diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 4904856..88c62d1 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -66,13 +66,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index dedecd7..57955df 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -63,13 +63,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1
/* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 0414cc3..4b4fb1a 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -67,13 +67,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 2 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1
/* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 86a4731..8864f3a 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -73,7 +73,7 @@ #define CONFIG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 -#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
/* * MMC Configs diff --git a/include/configs/qong.h b/include/configs/qong.h index 7cd9558..cbb53dd 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -56,14 +56,14 @@
#define CONFIG_MXC_SPI #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783
#define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 100000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
/* FPGA */ #define CONFIG_QONG_FPGA 1