TPS659038 is the power IC used in DRA7XX boards. Adding support for this and also adding pmic data for DRA7XX boards.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 23 ++++++++++++++ arch/arm/cpu/armv7/omap5/hw_data.c | 38 +++++++++++++++++++++++- arch/arm/include/asm/arch-omap4/sys_proto.h | 1 + arch/arm/include/asm/arch-omap5/clock.h | 15 ++++++++++ arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + arch/arm/include/asm/omap_common.h | 3 ++ 6 files changed, 80 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index a1ada58..dc57516 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -30,6 +30,7 @@ * MA 02111-1307 USA */ #include <common.h> +#include <i2c.h> #include <asm/omap_common.h> #include <asm/gpio.h> #include <asm/arch/clock.h> @@ -487,6 +488,9 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) u32 offset = volt_mv; int ret = 0;
+ if (!volt_mv) + return; + pmic->pmic_bus_init(); /* See if we can first get the GPIO if needed */ if (pmic->gpio_en) @@ -534,6 +538,15 @@ void scale_vcores(struct vcores_data const *vcores) do_scale_vcore(vcores->mm.addr, vcores->mm.value, vcores->mm.pmic);
+ do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, + vcores->gpu.pmic); + + do_scale_vcore(vcores->eve.addr, vcores->eve.value, + vcores->eve.pmic); + + do_scale_vcore(vcores->iva.addr, vcores->iva.value, + vcores->iva.pmic); + if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { /* Configure LDO SRAM "magic" bits */ writel(2, (*prcm)->prm_sldo_core_setup); @@ -723,3 +736,13 @@ void prcm_init(void) if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) enable_basic_uboot_clocks(); } + +void gpi2c_init(void) +{ + static int gpi2c = 1; + + if (gpi2c) { + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + gpi2c = 0; + } +} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 585e318..90274a0 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -26,6 +26,7 @@ * MA 02111-1307 USA */ #include <common.h> +#include <palmas.h> #include <asm/arch/omap.h> #include <asm/arch/sys_proto.h> #include <asm/omap_common.h> @@ -294,6 +295,19 @@ struct pmic_data palmas = { .pmic_write = omap_vc_bypass_send_value, };
+struct pmic_data tps659038 = { + .base_offset = PALMAS_SMPS_BASE_VOLT_UV, + .step = 10000, /* 10 mV represented in uV */ + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + .start_code = 6, + .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, + .pmic_bus_init = gpi2c_init, + .pmic_write = palmas_i2c_write_u8, +}; + struct vcores_data omap5430_volts = { .mpu.value = VDD_MPU, .mpu.addr = SMPS_REG_ADDR_12_MPU, @@ -322,6 +336,28 @@ struct vcores_data omap5430_volts_es2 = { .mm.pmic = &palmas, };
+struct vcores_data dra752_volts = { + .mpu.value = VDD_MPU_DRA752, + .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU, + .mpu.pmic = &tps659038, + + .eve.value = VDD_EVE_DRA752, + .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE, + .eve.pmic = &tps659038, + + .gpu.value = VDD_GPU_DRA752, + .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU, + .gpu.pmic = &tps659038, + + .core.value = VDD_CORE_DRA752, + .core.addr = TPS659038_REG_ADDR_SMPS7_CORE, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA752, + .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA, + .iva.pmic = &tps659038, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -562,7 +598,7 @@ void hw_data_init(void) case DRA752_ES1_0: *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; - *omap_vcores = &omap5430_volts_es2; + *omap_vcores = &dra752_volts; *ctrl = &dra7xx_ctrl; break;
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 38d4768..14479ba 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -57,6 +57,7 @@ u32 cortex_rev(void); void init_omap_revision(void); void do_io_settings(void); void sri2c_init(void); +void gpi2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 6673a02..f7ddd5f 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -212,9 +212,24 @@ #define VDD_MPU_ES2_LOW 880 #define VDD_MM_ES2_LOW 880
+/* TPS659038 Voltage settings in mv for OPP_NOMINAL */ +#define VDD_MPU_DRA752 1090 +#define VDD_EVE_DRA752 1060 +#define VDD_GPU_DRA752 1060 +#define VDD_CORE_DRA752 1030 +#define VDD_IVA_DRA752 1060 + /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000
+/* TPS659038 */ +#define TPS659038_I2C_SLAVE_ADDR 0x58 +#define TPS659038_REG_ADDR_SMPS12_MPU 0x23 +#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B +#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F +#define TPS659038_REG_ADDR_SMPS7_CORE 0x33 +#define TPS659038_REG_ADDR_SMPS8_IVA 0x37 + /* TPS */ #define TPS62361_I2C_SLAVE_ADDR 0x60 #define TPS62361_REG_ADDR_SET0 0x0 diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 52c2271..8f6f3bf 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -61,6 +61,7 @@ u32 cortex_rev(void); void init_omap_revision(void); void do_io_settings(void); void sri2c_init(void); +void gpi2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 3f1d31d..6b28f2e 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -510,6 +510,9 @@ struct vcores_data { struct volts mpu; struct volts core; struct volts mm; + struct volts gpu; + struct volts eve; + struct volts iva; };
extern struct prcm_regs const **prcm;