I was able to get SD Card booting for P2041RDB working correctly with U-Boot 2013.07. However, today I was attempting to move to 2013.10, and I'm having issues booting from the SD Card. Specifically issues with U-Boot not reading my FMan firmware binary file on the SD Card.
NOTE: all of the following steps works fine with 2013.07 so I'm wondering what changed to make this error happen.
The FMan binary I'm using is fsl_fman_ucode_p2041_r2.0_106_1_9.bin from the Freescale FMAN git repo. Below are the commands I used to build u-boot.
http://git.freescale.com/git/cgit.cgi/ppc/sdk/fm-ucode.git
Commands ---------- make P2041RDB_SDCARD_config make u-boot.pbl
The commands I used to format my SD Card (granted there is more to my SD card script than this):
# Partition Overview # 1 - (Empty) partition since u-boot.pbl is dd to block 8 # 2 - (FAT32) Boot - where the kernel/device tree are located # 3 - (EXT3) Rootfs { echo ,1,0x00,* echo ,9,0x0C,- echo ,,0x0C,- } | sfdisk -D -H 255 -S 63 -C $CYLINDERS $DRIVE
Then the commands to load my SD Card using dd:
sudo dd if=u-boot.pbl of=/dev/sdb bs=512 seek=8 sudo dd if=fsl_fman_ucode_p2041_r2.0_106_1_9.bin of=/dev/sdb bs=512 seek=1130
Boot log: -----------------------------
U-Boot 2013.10 (Oct 23 2013 - 11:23:12)
CPU0: P2041E, Version: 1.1, (0x82180111) Core: e500mc, Version: 2.2, (0x80230022) Clock Configuration: CPU0:1500 MHz, CPU1:1500 MHz, CPU2:1500 MHz, CPU3:1500 MHz, CCB:750 MHz, DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:93.750 MHz FMAN1: 583.333 MHz QMAN: 375 MHz PME: 375 MHz L1: D-cache 32 KiB enabled I-cache 32 KiB enabled Reset Configuration Word (RCW): 00000000: 12600000 00000000 241c0000 00000000 00000010: 649fa0c1 c3c02000 68000000 40000000 00000020: 00000000 00000000 00000000 d0030f07 00000030: 00000000 00000000 00000000 00000000 Board: P2041RDB, CPLD version: 4.1 vBank: 1 SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz I2C: ready SPI: ready DRAM: Initializing....using SPD Detected UDIMM UG51U6400N8SU-ACF 2 GiB left unmapped 4 GiB (DDR3, 64-bit, CL=9, ECC off) DDR Chip-Select Interleaving Mode: CS0+CS1 Testing 0x00000000 - 0x7fffffff Testing 0x80000000 - 0xffffffff Remap DDR 2 GiB left unmapped
POST memory PASSED Flash: 128 MiB L2: 128 KiB enabled Corenet Platform Cache: 1 MiB enabled SERDES: bank 3 disabled SRIO1: disabled SRIO2: disabled NAND: 512 MiB MMC: FSL_SDHC: 0 MMC: block number 0xfffffffe exceeds max(0x0) Using default environment
EEPROM: Invalid ID (ff ff ff ff) PCIe1: disabled PCIe2: Root Complex, no link, regs @ 0xfe201000 PCIe2: Bus 00 - 00 PCIe3: disabled In: serial Out: serial Err: serial Net: Initializing Fman
MMC read: dev # 0, block # 1130, count 128 ... MMC: block number 0x4ea exceeds max(0x0) Fman1: Data at 7fe32a80 is not a firmware No ethernet found. Hit any key to stop autoboot: 0
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I find it interesting that the block number that it attempts to read is 1258 when the line before that says that it is reading 1130.
Also interesting is this: MMC: FSL_SDHC: 0
Any help or insight would be useful. I haven't had a chance to dig into the issue to debug it further as I've revert back to 2013.07 for now. I will eventually get around to looking into.
Thanks, -Ryan
------------------------------------------------------------ Ryan J Barnett / Software Engineer / Platform SW MS 137-157, 855 35th St NE, Cedar Rapids, IA, 52498-3161, US rjbarnet@rockwellcollins.com www.rockwellcollins.com