On Sat, Jan 20, 2018 at 6:43 AM, Álvaro Fernández Rojas noltari@gmail.com wrote:
BCM63xx HSSPI controller has the same issue as BCM63xx SPI controller: it doesn't allow keeping CS active between transfers. However, this controller allows changing CS polarities, which is used in the linux upstream driver to manage CS as desired.
v6: Introduce changes suggested by Simon Glass:
- Fix defconfig order.
v5: Introduce changes suggested by Jagan Teki:
- Rename SPI_PP_ macros.
- cs_activate instead of claim_cs.
- deactivate_cs instead of release_cs.
- Use wait_for_bit_be32 instead of infinite loop.
v4: Sync with master. v3: Switch to CONFIG_BCM63XX_HSSPI and rebase on top of SPI v4. v2: Introduce changes suggested by Simon Glass:
- Split bcm63xx_hsspi_xfer() into smaller functions.
- Check possible clock errors.
- Check possible reset errors.
- Switch to devfdt_get_addr_size_index().
- Use setbits32_be() for clock gate.
Álvaro Fernández Rojas (4): dm: spi: add BCM63xx HSSPI driver mips: bmips: add bcm63xx-hsspi driver support for BCM6328 mips: bmips: add bcm63xx-hsspi driver support for BCM63268 mips: bmips: enable the SPI flash on the Comtrend AR-5387un
Applied to u-boot-spi/master, thanks!