From: Rick Chen rick@andestech.com
Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse and configure the cache settings (data & instruction prefetch, data & tag latency) from the device tree blob.
Also implement L2 cache flush and disable before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable
Rick Chen (6): dm: cache: add v5l2 cache controller driver riscv: ae350: use the v5l2 driver to configure the cache riscv: ae350: add imply v5l2 cache controller riscv: cache: Flush L2 cache before jump to linux riscv: dts: move out AE350 L2 node from cpus node riscv: ax25: use CCTL to flush d-cache
arch/riscv/cpu/ax25/cache.c | 22 ++++--- arch/riscv/cpu/ax25/cpu.c | 4 ++ arch/riscv/dts/ae350_32.dts | 17 ++++-- arch/riscv/dts/ae350_64.dts | 17 ++++-- arch/riscv/include/asm/global_data.h | 3 + arch/riscv/include/asm/v5l2cache.h | 61 +++++++++++++++++++ board/AndesTech/ax25-ae350/Kconfig | 1 + board/AndesTech/ax25-ae350/ax25-ae350.c | 15 +++++ drivers/cache/Kconfig | 9 +++ drivers/cache/Makefile | 1 + drivers/cache/cache-v5l2.c | 102 ++++++++++++++++++++++++++++++++ 11 files changed, 231 insertions(+), 21 deletions(-) create mode 100644 arch/riscv/include/asm/v5l2cache.h create mode 100644 drivers/cache/cache-v5l2.c