On Wed, 17 Jun 2020 at 00:57, Tom Rini trini@konsulko.com wrote:
On Wed, Jun 17, 2020 at 12:04:16AM +0300, Vladimir Oltean wrote:
On Wed, 17 Jun 2020 at 00:01, Vladimir Oltean olteanv@gmail.com wrote:
On Tue, 16 Jun 2020 at 23:58, Tom Rini trini@konsulko.com wrote:
On Tue, Jun 16, 2020 at 05:55:10PM -0300, Fabio Estevam wrote:
On Tue, Jun 16, 2020 at 5:51 PM Tom Rini trini@konsulko.com wrote:
Ah. So this is probably why the DT being right isn't helping then. If you want to blind-convert I'm happy to test, otherwise do you have a similar board conversion for me to look at? Thanks!
Please try Vladimir's suggestion as it seems to be the less intrusive approach:
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -321,7 +321,7 @@ int board_eth_init(bd_t *bis) if (!bus) return -EINVAL;
phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
phydev = phy_find_by_mask(bus, ETH_PHY_MASK,PHY_INTERFACE_MODE_RGMII_ID); if (!phydev) { ret = -EINVAL; goto free_bus;
OK, tried that and not enough. Console says PHY autoneg completes, but DHCP still doesn't reply.
What about with the manual revert in place? What does phydev->interface print? Not only in atheros.c, but also in mx6cuboxi.c, right below this phy_find_by_mask call. Trying to understand if this is your only problem or if there are more.
In fact there's one more 'manual' thing you can do.
For this test, based on your previous email and the kernel dts files, I made the change to mx6cuboxi.c to pass PHY_INTERFACE_MODE_RGMII_ID to phy_find_by_mask(...).
Check if RX delay is enabled (bit 15 of debug register 0): => mdio write eTSEC1 0x1D 0 => mdio read eTSEC1 0x1E => mdio write eTSEC1 0x1E <new value>
=> mdio list FEC: 0 - AR8035 <--> FEC => mdio write FEC 0x1D 0 => mdio read FEC 0x1E Reading from bus FEC PHY at address 0: 30 - 0x82ee ... so it's enabled already.
Check if TX delay is enabled (bit 8 of debug register 5): => mdio write eTSEC1 0x1D 5 => mdio read eTSEC1 0x1E => mdio write eTSEC1 0x1E <new value>
=> mdio write FEC 0x1D 5 => mdio read FEC 0x1E Reading from bus FEC PHY at address 0: 30 - 0x2d47 ... so it's enabled already.
Or did I make a mistake? Thanks!
-- Tom
Yes, the PHY has RGMII delays enabled in both directions.