On Sunday, October 22, 2006 4:13 AM Stefan Roese wrote:
However sdram0_mcsts register's most significant bit never becomes 1, meaning SDRAM controller cannot complete memory initialization and code stays in endless loop: That looks like HW problem for me.
Yes. I never have seen a board where this did not happen.
Now I pass sdram0_mcsts status check (our HW folks said there was some clock marginality they fixed) and proceed to program_tr1() function which fails:
U-Boot 1.1.4 (Oct 23 2006 - 20:28:01)
CPU: AMCC PowerPC 440EP Rev. B at 333.333 MHz (PLB=133, OPB=66, EBC=33 MHz) I2C boot EEPROM disabled Internal PCI arbiter disabled, PCI async ext clock used 32 kB I-Cache 32 kB D-Cache Board: Yosemite - AMCC PPC440EP Evaluation Board I2C: ready DRAM: get_spd_info banks 1 Addresses: 0x51 DIMM: slot 0: populated, bytes 128 size 8 DIMM: slot 0: DDR SDRAM detected DIMM: 0 voltage level supported. DIMM: sdram0_cfg0 0x02000000 -> 0x00000000 -> 0x04000000. DIMM: sdram0_cfg1 0x00000000 -> 0x00000000. DIMM: sdram0_rtr 0x04100000. DIMM: sdram0_tr0 0x00894012 -> 0x00000000 -> 0x408A4012. DIMM: sdram0_b0cr 0x000C6001 base 0x00000000 size 0x10000000. DIMM: sdram0_b1cr 0x100C6001 base 0x10000000 size 0x10000000. DIMM: total size 0x20000000 Starting memory test .... ERROR: Cannot determine a common read delay. ### ERROR ### Please RESET the board ###
I tried several hardcoded tr1 values, it doesn't work either - code crashes on read/write attempts - I must investigate where exactly by reviewing assembler - GDB debugging on C level was not very helpful. But I believe it still same HW problem - situation became better, yet not good enough...
Best regards, Leonid.