[U-Boot] [PATCH 5/9 V2] EXYNOS5: CLOCK: Add clock support for Exynos5250 Rev 1.0

20 Jun 2012

Add new clock values for Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali hatim.rv@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
---
Chnages in V2:
    - None
 board/samsung/smdk5250/clock_init.c |  714 ++++++++++++++++++++++++++++------
 board/samsung/smdk5250/clock_init.h |  149 ++++++++
 board/samsung/smdk5250/setup.h      |  718 +++++++++++++++++++----------------
 3 files changed, 1136 insertions(+), 445 deletions(-)
 create mode 100644 board/samsung/smdk5250/clock_init.h

diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c
index 305842d..2eba397 100644
--- a/board/samsung/smdk5250/clock_init.c
+++ b/board/samsung/smdk5250/clock_init.c
@@ -22,181 +22,643 @@
  * MA 02111-1307 USA
  */
+#include <common.h>
 #include <config.h>
-#include <version.h>
 #include <asm/io.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch/spl.h>
+
+#include "clock_init.h"
 #include "setup.h"
-void system_clock_init()
+DECLARE_GLOBAL_DATA_PTR;
+
+struct arm_clk_ratios arm_clk_ratios[] = {
+	{
+		.arm_freq_mhz = 600,
+
+		.apll_mdiv = 0xc8,
+		.apll_pdiv = 0x4,
+		.apll_sdiv = 0x1,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x1,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x2,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x1,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 800,
+
+		.apll_mdiv = 0x64,
+		.apll_pdiv = 0x3,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x1,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x3,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x2,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 1000,
+
+		.apll_mdiv = 0x7d,
+		.apll_pdiv = 0x3,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x1,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x4,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x2,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 1200,
+
+		.apll_mdiv = 0x96,
+		.apll_pdiv = 0x3,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x3,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x5,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x3,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 1400,
+
+		.apll_mdiv = 0xaf,
+		.apll_pdiv = 0x3,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x3,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x6,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x3,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 1700,
+
+		.apll_mdiv = 0x1a9,
+		.apll_pdiv = 0x6,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x3,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x6,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x3,
+		.arm_ratio = 0x0,
+	}
+};
+struct mem_timings mem_timings[] = {
+	{
+		.mem_manuf = MEM_MANUF_ELPIDA,
+		.mem_type = DDR_MODE_DDR3,
+		.frequency_mhz = 800,
+		.mpll_mdiv = 0xc8,
+		.mpll_pdiv = 0x3,
+		.mpll_sdiv = 0x0,
+		.cpll_mdiv = 0xde,
+		.cpll_pdiv = 0x4,
+		.cpll_sdiv = 0x2,
+		.gpll_mdiv = 0x215,
+		.gpll_pdiv = 0xc,
+		.gpll_sdiv = 0x1,
+		.epll_mdiv = 0x60,
+		.epll_pdiv = 0x3,
+		.epll_sdiv = 0x3,
+		.vpll_mdiv = 0x96,
+		.vpll_pdiv = 0x3,
+		.vpll_sdiv = 0x2,
+
+		.bpll_mdiv = 0x64,
+		.bpll_pdiv = 0x3,
+		.bpll_sdiv = 0x0,
+		.pclk_cdrex_ratio = 0x5,
+		.direct_cmd_msr = {
+			0x00020018, 0x00030000, 0x00010042, 0x00000d70
+		},
+		.timing_ref = 0x000000bb,
+		.timing_row = 0x8c36650e,
+		.timing_data = 0x3630580b,
+		.timing_power = 0x41000a44,
+		.phy0_dqs = 0x08080808,
+		.phy1_dqs = 0x08080808,
+		.phy0_dq = 0x08080808,
+		.phy1_dq = 0x08080808,
+		.phy0_tFS = 0x4,
+		.phy1_tFS = 0x4,
+		.phy0_pulld_dqs = 0xf,
+		.phy1_pulld_dqs = 0xf,
+
+		.lpddr3_ctrl_phy_reset = 0x1,
+		.ctrl_start_point = 0x10,
+		.ctrl_inc = 0x10,
+		.ctrl_start = 0x1,
+		.ctrl_dll_on = 0x1,
+		.ctrl_ref = 0x8,
+
+		.ctrl_force = 0x1a,
+		.ctrl_rdlat = 0x0b,
+		.ctrl_bstlen = 0x08,
+
+		.fp_resync = 0x8,
+		.iv_size = 0x7,
+		.dfi_init_start = 1,
+		.aref_en = 1,
+
+		.rd_fetch = 0x3,
+
+		.zq_mode_dds = 0x7,
+		.zq_mode_term = 0x1,
+		.zq_mode_noterm = 0,
+
+		/*
+		* Dynamic Clock: Always Running
+		* Memory Burst length: 8
+		* Number of chips: 1
+		* Memory Bus width: 32 bit
+		* Memory Type: DDR3
+		* Additional Latancy for PLL: 0 Cycle
+		*/
+		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+			DMC_MEMCONTROL_TP_DISABLE |
+			DMC_MEMCONTROL_DSREF_ENABLE |
+			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+			DMC_MEMCONTROL_NUM_CHIP_1 |
+			DMC_MEMCONTROL_BL_8 |
+			DMC_MEMCONTROL_PZQ_DISABLE |
+			DMC_MEMCONTROL_MRR_BYTE_7_0,
+		.memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
+			DMC_MEMCONFIGx_CHIP_COL_10 |
+			DMC_MEMCONFIGx_CHIP_ROW_15 |
+			DMC_MEMCONFIGx_CHIP_BANK_8,
+		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
+		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
+		.prechconfig_tp_cnt = 0xff,
+		.dpwrdn_cyc = 0xff,
+		.dsref_cyc = 0xffff,
+		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+			DMC_CONCONTROL_RD_FETCH_DISABLE |
+			DMC_CONCONTROL_EMPTY_DISABLE |
+			DMC_CONCONTROL_AREF_EN_DISABLE |
+			DMC_CONCONTROL_IO_PD_CON_DISABLE,
+		.dmc_channels = 2,
+		.chips_per_channel = 2,
+		.chips_to_configure = 1,
+		.send_zq_init = 1,
+		.impedance = IMP_OUTPUT_DRV_30_OHM,
+		.gate_leveling_enable = 0,
+	}, {
+		.mem_manuf = MEM_MANUF_SAMSUNG,
+		.mem_type = DDR_MODE_DDR3,
+		.frequency_mhz = 800,
+		.mpll_mdiv = 0xc8,
+		.mpll_pdiv = 0x3,
+		.mpll_sdiv = 0x0,
+		.cpll_mdiv = 0xde,
+		.cpll_pdiv = 0x4,
+		.cpll_sdiv = 0x2,
+		.gpll_mdiv = 0x215,
+		.gpll_pdiv = 0xc,
+		.gpll_sdiv = 0x1,
+		.epll_mdiv = 0x60,
+		.epll_pdiv = 0x3,
+		.epll_sdiv = 0x3,
+		.vpll_mdiv = 0x96,
+		.vpll_pdiv = 0x3,
+		.vpll_sdiv = 0x2,
+
+		.bpll_mdiv = 0x64,
+		.bpll_pdiv = 0x3,
+		.bpll_sdiv = 0x0,
+		.pclk_cdrex_ratio = 0x5,
+		.direct_cmd_msr = {
+			0x00020018, 0x00030000, 0x00010000, 0x00000d70
+		},
+		.timing_ref = 0x000000bb,
+		.timing_row = 0x8c36650e,
+		.timing_data = 0x3630580b,
+		.timing_power = 0x41000a44,
+		.phy0_dqs = 0x08080808,
+		.phy1_dqs = 0x08080808,
+		.phy0_dq = 0x08080808,
+		.phy1_dq = 0x08080808,
+		.phy0_tFS = 0x8,
+		.phy1_tFS = 0x8,
+		.phy0_pulld_dqs = 0xf,
+		.phy1_pulld_dqs = 0xf,
+
+		.lpddr3_ctrl_phy_reset = 0x1,
+		.ctrl_start_point = 0x10,
+		.ctrl_inc = 0x10,
+		.ctrl_start = 0x1,
+		.ctrl_dll_on = 0x1,
+		.ctrl_ref = 0x8,
+
+		.ctrl_force = 0x1a,
+		.ctrl_rdlat = 0x0b,
+		.ctrl_bstlen = 0x08,
+
+		.fp_resync = 0x8,
+		.iv_size = 0x7,
+		.dfi_init_start = 1,
+		.aref_en = 1,
+
+		.rd_fetch = 0x3,
+
+		.zq_mode_dds = 0x5,
+		.zq_mode_term = 0x1,
+		.zq_mode_noterm = 1,
+
+		/*
+		* Dynamic Clock: Always Running
+		* Memory Burst length: 8
+		* Number of chips: 1
+		* Memory Bus width: 32 bit
+		* Memory Type: DDR3
+		* Additional Latancy for PLL: 0 Cycle
+		*/
+		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+			DMC_MEMCONTROL_TP_DISABLE |
+			DMC_MEMCONTROL_DSREF_ENABLE |
+			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+			DMC_MEMCONTROL_NUM_CHIP_1 |
+			DMC_MEMCONTROL_BL_8 |
+			DMC_MEMCONTROL_PZQ_DISABLE |
+			DMC_MEMCONTROL_MRR_BYTE_7_0,
+		.memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
+			DMC_MEMCONFIGx_CHIP_COL_10 |
+			DMC_MEMCONFIGx_CHIP_ROW_15 |
+			DMC_MEMCONFIGx_CHIP_BANK_8,
+		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
+		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
+		.prechconfig_tp_cnt = 0xff,
+		.dpwrdn_cyc = 0xff,
+		.dsref_cyc = 0xffff,
+		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+			DMC_CONCONTROL_RD_FETCH_DISABLE |
+			DMC_CONCONTROL_EMPTY_DISABLE |
+			DMC_CONCONTROL_AREF_EN_DISABLE |
+			DMC_CONCONTROL_IO_PD_CON_DISABLE,
+		.dmc_channels = 2,
+		.chips_per_channel = 2,
+		.chips_to_configure = 1,
+		.send_zq_init = 1,
+		.impedance = IMP_OUTPUT_DRV_40_OHM,
+		.gate_leveling_enable = 1,
+	}
+};
+
+/**
+ * Get the required memory type and speed (SPL version).
+ *
+ * In SPL we have no device tree, so we use the machine parameters
+ *
+ * @param mem_type	Returns memory type
+ * @param frequency_mhz	Returns memory speed in MHz
+ * @param arm_freq	Returns ARM clock speed in MHz
+ * @param mem_manuf	Return Memory Manufacturer name
+ * @return 0 if all ok
+ */
+static int clock_get_mem_selection(enum ddr_mode *mem_type,
+		unsigned *frequency_mhz, unsigned *arm_freq,
+		enum mem_manuf *mem_manuf)
 {
-	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+	struct spl_machine_param *params;
-	/*
-	 * MUX_APLL_SEL[0]: FINPLL = 0
-	 * MUX_CPU_SEL[6]: MOUTAPLL = 0
-	 * MUX_HPM_SEL[20]: MOUTAPLL = 0
-	 */
-	writel(0x0, &clk->src_cpu);
+	params = spl_get_machine_params();
+	*mem_type = params->mem_type;
+	*frequency_mhz = params->frequency_mhz;
+	*arm_freq = params->arm_freq_mhz;
+	*mem_manuf = params->mem_manuf;
-	/* MUX_MPLL_SEL[8]: FINPLL = 0 */
-	writel(0x0, &clk->src_core1);
+	return 0;
+}
-	/*
-	 * VPLLSRC_SEL[0]: FINPLL = 0
-	 * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: FINPLL = 0
-	 */
-	writel(0x0, &clk->src_top2);
+/* Get the ratios for setting ARM clock */
+struct arm_clk_ratios *get_arm_ratios(void)
+{
+	struct arm_clk_ratios *arm_ratio;
+	enum ddr_mode mem_type;
+	enum mem_manuf mem_manuf;
+	unsigned frequency_mhz, arm_freq;
+	int i;
+
+	if (clock_get_mem_selection(&mem_type, &frequency_mhz,
+					&arm_freq, &mem_manuf))
+		;
+	for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
+		i++, arm_ratio++) {
+		if (arm_ratio->arm_freq_mhz == arm_freq)
+			return arm_ratio;
+	}
+
+	/* will hang if failed to find clock ratio */
+	while (1)
+		;
+
+	return NULL;
+}
-	/* MUX_BPLL_SEL[0]: FINPLL = 0 */
-	writel(0x0, &clk->src_cdrex);
+struct mem_timings *clock_get_mem_timings(void)
+{
+	struct mem_timings *mem;
+	enum ddr_mode mem_type;
+	enum mem_manuf mem_manuf;
+	unsigned frequency_mhz, arm_freq;
+	int i;
+
+	if (!clock_get_mem_selection(&mem_type, &frequency_mhz,
+						&arm_freq, &mem_manuf)) {
+		for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
+				i++, mem++) {
+			if (mem->mem_type == mem_type &&
+					mem->frequency_mhz == frequency_mhz &&
+					mem->mem_manuf == mem_manuf)
+				return mem;
+		}
+	}
+
+	/* will hang if failed to find memory timings */
+	while (1)
+		;
+
+	return NULL;
+}
-	/* MUX_ACLK_* Clock Selection */
-	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+void system_clock_init()
+{
+	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+	struct mem_timings *mem;
+	struct arm_clk_ratios *arm_clk_ratio;
+	u32 val, tmp;
+
+	mem = clock_get_mem_timings();
+	arm_clk_ratio = get_arm_ratios();
+
+	clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
+	do {
+		val = readl(&clk->mux_stat_cpu);
+	} while ((val | MUX_APLL_SEL_MASK) != val);
+
+	clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
+	do {
+		val = readl(&clk->mux_stat_core1);
+	} while ((val | MUX_MPLL_SEL_MASK) != val);
+
+	clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK);
+	clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK);
+	clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK);
+	clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK);
+	tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
+		| MUX_GPLL_SEL_MASK;
+	do {
+		val = readl(&clk->mux_stat_top2);
+	} while ((val | tmp) != val);
+
+	clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
+	do {
+		val = readl(&clk->mux_stat_cdrex);
+	} while ((val | MUX_BPLL_SEL_MASK) != val);
-	/* MUX_ACLK_* Clock Selection */
-	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+	/* PLL locktime */
+	writel(APLL_LOCK_VAL, &clk->apll_lock);
-	/* MUX_ACLK_* Clock Selection */
-	writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
+	writel(MPLL_LOCK_VAL, &clk->mpll_lock);
-	/* MUX_PWI_SEL[19:16]: SCLKMPLL = 6 */
-	writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
+	writel(BPLL_LOCK_VAL, &clk->bpll_lock);
-	/* MUX_ATCLK_LEX[0]: ACLK_200 = 0 */
-	writel(CLK_SRC_LEX_VAL, &clk->src_lex);
+	writel(CPLL_LOCK_VAL, &clk->cpll_lock);
-	/* UART [0-5]: SCLKMPLL = 6 */
-	writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+	writel(GPLL_LOCK_VAL, &clk->gpll_lock);
-	/* Set Clock Ratios */
-	writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+	writel(EPLL_LOCK_VAL, &clk->epll_lock);
-	/* Set COPY and HPM Ratio */
-	writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+	writel(VPLL_LOCK_VAL, &clk->vpll_lock);
-	/* CORED_RATIO, COREP_RATIO */
-	writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
+	writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
+
+	writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
+	do {
+		val = readl(&clk->mux_stat_cpu);
+	} while ((val | HPM_SEL_SCLK_MPLL) != val);
+
+	val = arm_clk_ratio->arm2_ratio << 28
+		| arm_clk_ratio->apll_ratio << 24
+		| arm_clk_ratio->pclk_dbg_ratio << 20
+		| arm_clk_ratio->atb_ratio << 16
+		| arm_clk_ratio->periph_ratio << 12
+		| arm_clk_ratio->acp_ratio << 8
+		| arm_clk_ratio->cpud_ratio << 4
+		| arm_clk_ratio->arm_ratio;
+	writel(val, &clk->div_cpu0);
+	do {
+		val = readl(&clk->div_stat_cpu0);
+	} while (0 != val);
-	/* PWI_RATIO[11:8], DVSEM_RATIO[22:16], DPM_RATIO[24:20] */
-	writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
+	writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+	do {
+		val = readl(&clk->div_stat_cpu1);
+	} while (0 != val);
-	/* ACLK_*_RATIO */
-	writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+	/* Set APLL */
+	writel(APLL_CON1_VAL, &clk->apll_con1);
+	val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
+			arm_clk_ratio->apll_sdiv);
+	writel(val, &clk->apll_con0);
+	while (readl(&clk->apll_con0) & APLL_CON0_LOCKED)
+		;
-	/* ACLK_*_RATIO */
-	writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+	/* Set MPLL */
+	writel(MPLL_CON1_VAL, &clk->mpll_con1);
+	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
+	writel(val, &clk->mpll_con0);
+	while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED)
+		;
-	/* CDREX Ratio */
-	writel(CLK_DIV_CDREX_INIT_VAL, &clk->div_cdrex);
+	/* Set BPLL */
+	writel(BPLL_CON1_VAL, &clk->bpll_con1);
+	val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
+	writel(val, &clk->bpll_con0);
+	while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED)
+		;
-	/* MCLK_EFPHY_RATIO[3:0] */
-	writel(CLK_DIV_CDREX2_VAL, &clk->div_cdrex2);
+	/* Set CPLL */
+	writel(CPLL_CON1_VAL, &clk->cpll_con1);
+	val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
+	writel(val, &clk->cpll_con0);
+	while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED)
+		;
+
+	/* Set GPLL */
+	writel(GPLL_CON1_VAL, &clk->gpll_con1);
+	val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
+	writel(val, &clk->gpll_con0);
+	while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED)
+		;
-	/* {PCLK[4:6]|ATCLK[10:8]}_RATIO */
-	writel(CLK_DIV_LEX_VAL, &clk->div_lex);
+	/* Set EPLL */
+	writel(EPLL_CON2_VAL, &clk->epll_con2);
+	writel(EPLL_CON1_VAL, &clk->epll_con1);
+	val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
+	writel(val, &clk->epll_con0);
+	while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED)
+		;
-	/* PCLK_R0X_RATIO[3:0] */
-	writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+	/* Set VPLL */
+	writel(VPLL_CON2_VAL, &clk->vpll_con2);
+	writel(VPLL_CON1_VAL, &clk->vpll_con1);
+	val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
+	writel(val, &clk->vpll_con0);
+	while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED)
+		;
-	/* PCLK_R1X_RATIO[3:0] */
-	writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
+	writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
+	writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
+	while (readl(&clk->div_stat_core0) != 0)
+		;
-	/* SATA[24]: SCLKMPLL=0, MMC[0-4]: SCLKMPLL = 6 */
-	writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
+	writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
+	while (readl(&clk->div_stat_core1) != 0)
+		;
-	/* UART[0-4] */
-	writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
+	writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
+	while (readl(&clk->div_stat_sysrgt) != 0)
+		;
-	/* PWM_RATIO[3:0] */
-	writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
+	writel(CLK_DIV_ACP_VAL, &clk->div_acp);
+	while (readl(&clk->div_stat_acp) != 0)
+		;
-	/* SATA_RATIO, USB_DRD_RATIO */
-	writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+	writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
+	while (readl(&clk->div_stat_syslft) != 0)
+		;
-	/* MMC[0-1] */
-	writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+	writel(TOP2_VAL, &clk->src_top2);
+	writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
-	/* MMC[2-3] */
-	writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+	writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+	while (readl(&clk->div_stat_top0))
+		;
-	/* MMC[4] */
-	writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
+	writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+	while (readl(&clk->div_stat_top1))
+		;
-	/* ACLK|PLCK_ACP_RATIO */
-	writel(CLK_DIV_ACP_VAL, &clk->div_acp);
+	writel(CLK_SRC_LEX_VAL, &clk->src_lex);
+	while (1) {
+		val = readl(&clk->mux_stat_lex);
+		if (val == (val | 1))
+			break;
+	}
-	/* ISPDIV0_RATIO, ISPDIV1_RATIO */
-	writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+	writel(CLK_DIV_LEX_VAL, &clk->div_lex);
+	while (readl(&clk->div_stat_lex))
+		;
-	/* MCUISPDIV0_RATIO, MCUISPDIV1_RATIO */
-	writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+	writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+	while (readl(&clk->div_stat_r0x))
+		;
-	/* MPWMDIV_RATIO */
-	writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
+	writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+	while (readl(&clk->div_stat_r0x))
+		;
-	/* PLL locktime */
-	writel(APLL_LOCK_VAL, &clk->apll_lock);
+	writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
+	while (readl(&clk->div_stat_r1x))
+		;
-	writel(MPLL_LOCK_VAL, &clk->mpll_lock);
+	writel(CLK_REG_DISABLE, &clk->src_cdrex);
-	writel(BPLL_LOCK_VAL, &clk->bpll_lock);
+	writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
+	while (readl(&clk->div_stat_cdrex))
+		;
-	writel(CPLL_LOCK_VAL, &clk->cpll_lock);
+	val = readl(&clk->src_cpu);
+	val |= CLK_SRC_CPU_VAL;
+	writel(val, &clk->src_cpu);
-	writel(EPLL_LOCK_VAL, &clk->epll_lock);
+	val = readl(&clk->src_top2);
+	val |= CLK_SRC_TOP2_VAL;
+	writel(val, &clk->src_top2);
-	writel(VPLL_LOCK_VAL, &clk->vpll_lock);
+	val = readl(&clk->src_core1);
+	val |= CLK_SRC_CORE1_VAL;
+	writel(val, &clk->src_core1);
-	sdelay(0x10000);
+	writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
+	writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+	while (readl(&clk->div_stat_fsys0))
+		;
+
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
-	/* Set APLL */
-	writel(APLL_CON1_VAL, &clk->apll_con1);
-	writel(APLL_CON0_VAL, &clk->apll_con0);
-	sdelay(0x30000);
+	writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+	writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
-	/* Set MPLL */
-	writel(MPLL_CON1_VAL, &clk->mpll_con1);
-	writel(MPLL_CON0_VAL, &clk->mpll_con0);
-	sdelay(0x30000);
-	writel(BPLL_CON1_VAL, &clk->bpll_con1);
-	writel(BPLL_CON0_VAL, &clk->bpll_con0);
-	sdelay(0x30000);
+	writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
+	writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
+	writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
+	writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
+	writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
+	writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+	writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+	writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
-	/* Set CPLL */
-	writel(CPLL_CON1_VAL, &clk->cpll_con1);
-	writel(CPLL_CON0_VAL, &clk->cpll_con0);
-	sdelay(0x30000);
+	/* FIMD1 SRC CLK SELECTION */
+	writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
-	/* Set EPLL */
-	writel(EPLL_CON2_VAL, &clk->epll_con2);
-	writel(EPLL_CON1_VAL, &clk->epll_con1);
-	writel(EPLL_CON0_VAL, &clk->epll_con0);
-	sdelay(0x30000);
+	val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
+		| MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
+		| MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
+		| MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
+	writel(val, &clk->div_fsys2);
+}
-	/* Set VPLL */
-	writel(VPLL_CON2_VAL, &clk->vpll_con2);
-	writel(VPLL_CON1_VAL, &clk->vpll_con1);
-	writel(VPLL_CON0_VAL, &clk->vpll_con0);
-	sdelay(0x30000);
+void clock_init_dp_clock(void)
+{
+	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
-	/* Set MPLL */
-	/* After Initiallising th PLL select the sources accordingly */
-	/* MUX_APLL_SEL[0]: MOUTAPLLFOUT = 1 */
-	writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
-
-	/* MUX_MPLL_SEL[8]: MOUTMPLLFOUT = 1 */
-	writel(CLK_SRC_CORE1_VAL, &clk->src_core1);
-
-	/* MUX_BPLL_SEL[0]: FOUTBPLL = 1*/
-	writel(CLK_SRC_CDREX_INIT_VAL, &clk->src_cdrex);
-
-	/*
-	 * VPLLSRC_SEL[0]: FINPLL = 0
-	 * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: MOUT{CPLL|EPLL|VPLL} = 1
-	 * MUX_{MPLL[20]}|{BPLL[24]}_USER_SEL: FOUT{MPLL|BPLL} = 1
-	 */
-	writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
+	/* DP clock enable */
+	setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
+
+	/* We run DP at 267 Mhz */
+	setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
 }
diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h
new file mode 100644
index 0000000..f751bcb
--- /dev/null
+++ b/board/samsung/smdk5250/clock_init.h
@@ -0,0 +1,149 @@
+/*
+ * Clock initialization routines
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXYNOS_CLOCK_INIT_H
+#define __EXYNOS_CLOCK_INIT_H
+
+enum {
+	MEM_TIMINGS_MSR_COUNT	= 4,
+};
+
+/* These are the ratio's for configuring ARM clock */
+struct arm_clk_ratios {
+	unsigned arm_freq_mhz;		/* Frequency of ARM core in MHz */
+
+	unsigned apll_mdiv;
+	unsigned apll_pdiv;
+	unsigned apll_sdiv;
+
+	unsigned arm2_ratio;
+	unsigned apll_ratio;
+	unsigned pclk_dbg_ratio;
+	unsigned atb_ratio;
+	unsigned periph_ratio;
+	unsigned acp_ratio;
+	unsigned cpud_ratio;
+	unsigned arm_ratio;
+};
+
+/* These are the memory timings for a particular memory type and speed */
+struct mem_timings {
+	enum mem_manuf mem_manuf;	/* Memory manufacturer */
+	enum ddr_mode mem_type;		/* Memory type */
+	unsigned frequency_mhz;		/* Frequency of memory in MHz */
+
+	/* Here follow the timing parameters for the selected memory */
+	unsigned apll_mdiv;
+	unsigned apll_pdiv;
+	unsigned apll_sdiv;
+	unsigned mpll_mdiv;
+	unsigned mpll_pdiv;
+	unsigned mpll_sdiv;
+	unsigned cpll_mdiv;
+	unsigned cpll_pdiv;
+	unsigned cpll_sdiv;
+	unsigned gpll_mdiv;
+	unsigned gpll_pdiv;
+	unsigned gpll_sdiv;
+	unsigned epll_mdiv;
+	unsigned epll_pdiv;
+	unsigned epll_sdiv;
+	unsigned vpll_mdiv;
+	unsigned vpll_pdiv;
+	unsigned vpll_sdiv;
+	unsigned bpll_mdiv;
+	unsigned bpll_pdiv;
+	unsigned bpll_sdiv;
+	unsigned pclk_cdrex_ratio;
+	unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
+
+	unsigned timing_ref;
+	unsigned timing_row;
+	unsigned timing_data;
+	unsigned timing_power;
+
+	/* DQS, DQ, DEBUG offsets */
+	unsigned phy0_dqs;
+	unsigned phy1_dqs;
+	unsigned phy0_dq;
+	unsigned phy1_dq;
+	unsigned phy0_tFS;
+	unsigned phy1_tFS;
+	unsigned phy0_pulld_dqs;
+	unsigned phy1_pulld_dqs;
+
+	unsigned lpddr3_ctrl_phy_reset;
+	unsigned ctrl_start_point;
+	unsigned ctrl_inc;
+	unsigned ctrl_start;
+	unsigned ctrl_dll_on;
+	unsigned ctrl_ref;
+
+	unsigned ctrl_force;
+	unsigned ctrl_rdlat;
+	unsigned ctrl_bstlen;
+
+	unsigned fp_resync;
+	unsigned iv_size;
+	unsigned dfi_init_start;
+	unsigned aref_en;
+
+	unsigned rd_fetch;
+
+	unsigned zq_mode_dds;
+	unsigned zq_mode_term;
+	unsigned zq_mode_noterm;	/* 1 to allow termination disable */
+
+	unsigned memcontrol;
+	unsigned memconfig;
+
+	unsigned membaseconfig0;
+	unsigned membaseconfig1;
+	unsigned prechconfig_tp_cnt;
+	unsigned dpwrdn_cyc;
+	unsigned dsref_cyc;
+	unsigned concontrol;
+	/* Channel and Chip Selection */
+	uint8_t dmc_channels;		/* number of memory channels */
+	uint8_t chips_per_channel;	/* number of chips per channel */
+	uint8_t chips_to_configure;	/* number of chips to configure */
+	uint8_t send_zq_init;		/* 1 to send this command */
+	unsigned impedance;		/* drive strength impedeance */
+	uint8_t gate_leveling_enable;	/* check gate leveling is enabled */
+};
+
+/**
+ * Get the correct memory timings for our selected memory type and speed.
+ *
+ * This function can be called from SPL or the main U-Boot.
+ *
+ * @return pointer to the memory timings that we should use
+ */
+struct mem_timings *clock_get_mem_timings(void);
+
+/*
+ * Initialize clock for the device
+ */
+void system_clock_init(void);
+#endif
diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h
index 1276fd3..a0b71ce 100644
--- a/board/samsung/smdk5250/setup.h
+++ b/board/samsung/smdk5250/setup.h
@@ -1,5 +1,5 @@
 /*
- * Machine Specific Values for SMDK5250 board based on S5PC520
+ * Machine Specific Values for SMDK5250 board based on EXYNOS5
  *
  * Copyright (C) 2012 Samsung Electronics
  *
@@ -26,12 +26,6 @@
 #define _SMDK5250_SETUP_H
#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-
-/* GPIO Offsets for UART: GPIO Contol Register */
-#define EXYNOS5_GPIO_A0_CON_OFFSET	0x0
-#define EXYNOS5_GPIO_A1_CON_OFFSET	0x20
/* TZPC : Register Offsets */
 #define TZPC0_BASE		0x10100000
@@ -45,295 +39,418 @@
 #define TZPC8_BASE		0x10180000
 #define TZPC9_BASE		0x10190000
-/* CLK_SRC_CPU */
-/* 0 = MOUTAPLL, 1 = SCLKMPLL */
-#define MUX_HPM_SEL		0
-#define MUX_CPU_SEL		0
-#define MUX_APLL_SEL		1
-#define CLK_SRC_CPU_VAL		((MUX_HPM_SEL << 20) \
-				| (MUX_CPU_SEL << 16) \
-				| (MUX_APLL_SEL))
-
-/* CLK_DIV_CPU0 */
-#define ARM2_RATIO		0x0
-#define APLL_RATIO		0x1
-#define PCLK_DBG_RATIO		0x1
-#define ATB_RATIO		0x4
-#define PERIPH_RATIO		0x7
-#define ACP_RATIO		0x7
-#define CPUD_RATIO		0x2
-#define ARM_RATIO		0x0
-#define CLK_DIV_CPU0_VAL	((ARM2_RATIO << 28) \
-				| (APLL_RATIO << 24) \
-				| (PCLK_DBG_RATIO << 20) \
-				| (ATB_RATIO << 16) \
-				| (PERIPH_RATIO << 12) \
-				| (ACP_RATIO << 8) \
-				| (CPUD_RATIO << 4) \
-				| (ARM_RATIO))
-
-/* CLK_DIV_CPU1 */
-#define HPM_RATIO		0x4
-#define COPY_RATIO		0x0
-#define CLK_DIV_CPU1_VAL	((HPM_RATIO << 4) \
-				| (COPY_RATIO))
-
-#define APLL_MDIV		0x7D
-#define APLL_PDIV		0x3
-#define APLL_SDIV		0x0
-
-#define MPLL_MDIV		0x64
-#define MPLL_PDIV		0x3
-#define MPLL_SDIV		0x0
-
-#define CPLL_MDIV		0x96
-#define CPLL_PDIV		0x4
-#define CPLL_SDIV		0x0
-
-/* APLL_CON1 */
+/* APLL_CON1	*/
 #define APLL_CON1_VAL	(0x00203800)
-/* MPLL_CON1 */
-#define MPLL_CON1_VAL	(0x00203800)
+/* MPLL_CON1	*/
+#define MPLL_CON1_VAL   (0x00203800)
-/* CPLL_CON1 */
+/* CPLL_CON1	*/
 #define CPLL_CON1_VAL	(0x00203800)
-#define EPLL_MDIV	0x60
-#define EPLL_PDIV	0x3
-#define EPLL_SDIV	0x3
+/* GPLL_CON1	*/
+#define GPLL_CON1_VAL	(0x00203800)
+/* EPLL_CON1, CON2	*/
 #define EPLL_CON1_VAL	0x00000000
 #define EPLL_CON2_VAL	0x00000080
-#define VPLL_MDIV	0x96
-#define VPLL_PDIV	0x3
-#define VPLL_SDIV	0x2
-
+/* VPLL_CON1, CON2	*/
 #define VPLL_CON1_VAL	0x00000000
 #define VPLL_CON2_VAL	0x00000080
-#define BPLL_MDIV	0x215
-#define BPLL_PDIV	0xC
-#define BPLL_SDIV	0x1
-
+/* BPLL_CON1	*/
 #define BPLL_CON1_VAL	0x00203800
/* Set PLL */
 #define set_pll(mdiv, pdiv, sdiv)	(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
-#define APLL_CON0_VAL	set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
-#define MPLL_CON0_VAL	set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
-#define CPLL_CON0_VAL	set_pll(CPLL_MDIV, CPLL_PDIV, CPLL_SDIV)
-#define EPLL_CON0_VAL	set_pll(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
-#define VPLL_CON0_VAL	set_pll(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
-#define BPLL_CON0_VAL	set_pll(BPLL_MDIV, BPLL_PDIV, BPLL_SDIV)
+/* CLK_SRC_CPU	*/
+/* 0 = MOUTAPLL,  1 = SCLKMPLL	*/
+#define MUX_HPM_SEL             0
+#define MUX_CPU_SEL             0
+#define MUX_APLL_SEL            1
+
+#define CLK_SRC_CPU_VAL		((MUX_HPM_SEL << 20)    \
+				| (MUX_CPU_SEL << 16)  \
+				| (MUX_APLL_SEL))
+
+/* MEMCONTROL register bit fields */
+#define DMC_MEMCONTROL_CLK_STOP_DISABLE	(0 << 0)
+#define DMC_MEMCONTROL_DPWRDN_DISABLE	(0 << 1)
+#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE	(0 << 2)
+#define DMC_MEMCONTROL_TP_DISABLE	(0 << 4)
+#define DMC_MEMCONTROL_DSREF_DISABLE	(0 << 5)
+#define DMC_MEMCONTROL_DSREF_ENABLE	(1 << 5)
+#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x)    (x << 6)
+
+#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3  (7 << 8)
+#define DMC_MEMCONTROL_MEM_TYPE_DDR3    (6 << 8)
+#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2  (5 << 8)
+
+#define DMC_MEMCONTROL_MEM_WIDTH_32BIT  (2 << 12)
+
+#define DMC_MEMCONTROL_NUM_CHIP_1       (0 << 16)
+#define DMC_MEMCONTROL_NUM_CHIP_2       (1 << 16)
+
+#define DMC_MEMCONTROL_BL_8             (3 << 20)
+#define DMC_MEMCONTROL_BL_4             (2 << 20)
+
+#define DMC_MEMCONTROL_PZQ_DISABLE      (0 << 24)
+
+#define DMC_MEMCONTROL_MRR_BYTE_7_0     (0 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_15_8    (1 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_23_16   (2 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_31_24   (3 << 25)
+
+/* MEMCONFIG0 register bit fields */
+#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED     (1 << 12)
+#define DMC_MEMCONFIGx_CHIP_COL_10              (3 << 8)
+#define DMC_MEMCONFIGx_CHIP_ROW_14              (2 << 4)
+#define DMC_MEMCONFIGx_CHIP_ROW_15              (3 << 4)
+#define DMC_MEMCONFIGx_CHIP_BANK_8              (3 << 0)
+
+#define DMC_MEMBASECONFIGx_CHIP_BASE(x)         (x << 16)
+#define DMC_MEMBASECONFIGx_CHIP_MASK(x)         (x << 0)
+#define DMC_MEMBASECONFIG_VAL(x)        (       \
+	DMC_MEMBASECONFIGx_CHIP_BASE(x) |       \
+	DMC_MEMBASECONFIGx_CHIP_MASK(0x780)     \
+)
+
+#define DMC_MEMBASECONFIG0_VAL  DMC_MEMBASECONFIG_VAL(0x40)
+#define DMC_MEMBASECONFIG1_VAL  DMC_MEMBASECONFIG_VAL(0x80)
+
+#define DMC_PRECHCONFIG_VAL             0xFF000000
+#define DMC_PWRDNCONFIG_VAL             0xFFFF00FF
+
+#define DMC_CONCONTROL_RESET_VAL	0x0FFF0000
+#define DFI_INIT_START		(1 << 28)
+#define EMPTY			(1 << 8)
+#define AREF_EN			(1 << 5)
+
+#define DFI_INIT_COMPLETE_CHO	(1 << 2)
+#define DFI_INIT_COMPLETE_CH1	(1 << 3)
+
+#define RDLVL_COMPLETE_CHO	(1 << 14)
+#define RDLVL_COMPLETE_CH1	(1 << 15)
+
+#define CLK_STOP_EN	(1 << 0)
+#define DPWRDN_EN	(1 << 1)
+#define DSREF_EN	(1 << 5)
+
+/* COJCONTROL register bit fields */
+#define DMC_CONCONTROL_IO_PD_CON_DISABLE	(0 << 3)
+#define DMC_CONCONTROL_AREF_EN_DISABLE		(0 << 5)
+#define DMC_CONCONTROL_EMPTY_DISABLE		(0 << 8)
+#define DMC_CONCONTROL_EMPTY_ENABLE		(1 << 8)
+#define DMC_CONCONTROL_RD_FETCH_DISABLE		(0x0 << 12)
+#define DMC_CONCONTROL_TIMEOUT_LEVEL0		(0xFFF << 16)
+#define DMC_CONCONTROL_DFI_INIT_START_DISABLE	(0 << 28)
+
+/* CLK_DIV_CPU0_VAL */
+#define CLK_DIV_CPU0_VAL	((ARM2_RATIO << 28)             \
+				| (APLL_RATIO << 24)            \
+				| (PCLK_DBG_RATIO << 20)        \
+				| (ATB_RATIO << 16)             \
+				| (PERIPH_RATIO << 12)          \
+				| (ACP_RATIO << 8)              \
+				| (CPUD_RATIO << 4)             \
+				| (ARM_RATIO))
+
+
+/* CLK_FSYS */
+#define CLK_SRC_FSYS0_VAL              0x66666
+#define CLK_DIV_FSYS0_VAL	       0x0BB00000
+
+/* CLK_DIV_CPU1	*/
+#define HPM_RATIO               0x2
+#define COPY_RATIO              0x0
+
+/* CLK_DIV_CPU1 = 0x00000003 */
+#define CLK_DIV_CPU1_VAL        ((HPM_RATIO << 4)		\
+				| (COPY_RATIO))
/* CLK_SRC_CORE0 */
-#define CLK_SRC_CORE0_VAL	0x00060000
+#define CLK_SRC_CORE0_VAL       0x00000000
/* CLK_SRC_CORE1 */
-#define CLK_SRC_CORE1_VAL	0x100
+#define CLK_SRC_CORE1_VAL       0x100
/* CLK_DIV_CORE0 */
-#define CLK_DIV_CORE0_VAL	0x120000
+#define CLK_DIV_CORE0_VAL       0x00120000
/* CLK_DIV_CORE1 */
-#define CLK_DIV_CORE1_VAL	0x07070700
+#define CLK_DIV_CORE1_VAL       0x07070700
+
+/* CLK_DIV_SYSRGT */
+#define CLK_DIV_SYSRGT_VAL      0x00000111
+
+/* CLK_DIV_ACP */
+#define CLK_DIV_ACP_VAL         0x12
+
+/* CLK_DIV_SYSLFT */
+#define CLK_DIV_SYSLFT_VAL      0x00000311
/* CLK_SRC_CDREX */
-#define CLK_SRC_CDREX_INIT_VAL	0x1
-#define CLK_SRC_CDREX_VAL	0x111
+#define CLK_SRC_CDREX_VAL       0x1
/* CLK_DIV_CDREX */
-#define CLK_DIV_CDREX_INIT_VAL	0x71771111
-
-#define MCLK_CDREX2_RATIO	0x0
-#define ACLK_EFCON_RATIO	0x1
-#define MCLK_DPHY_RATIO		0x0
-#define MCLK_CDREX_RATIO	0x0
+#define MCLK_CDREX2_RATIO       0x0
+#define ACLK_EFCON_RATIO        0x1
+#define MCLK_DPHY_RATIO		0x1
+#define MCLK_CDREX_RATIO	0x1
 #define ACLK_C2C_200_RATIO	0x1
 #define C2C_CLK_400_RATIO	0x1
-#define PCLK_CDREX_RATIO	0x3
+#define PCLK_CDREX_RATIO	0x1
 #define ACLK_CDREX_RATIO	0x1
-#define CLK_DIV_CDREX_VAL	((MCLK_DPHY_RATIO << 20) \
-				| (MCLK_CDREX_RATIO << 16) \
-				| (ACLK_C2C_200_RATIO << 12) \
-				| (C2C_CLK_400_RATIO << 8) \
-				| (PCLK_CDREX_RATIO << 4) \
-				| (ACLK_CDREX_RATIO))
-#define MCLK_EFPHY_RATIO	0x4
-#define CLK_DIV_CDREX2_VAL	MCLK_EFPHY_RATIO
+#define CLK_DIV_CDREX_VAL	((MCLK_DPHY_RATIO << 24)        \
+				| (C2C_CLK_400_RATIO << 6)	\
+				| (PCLK_CDREX_RATIO << 4)	\
+				| (ACLK_CDREX_RATIO))
-/* CLK_DIV_ACP */
-#define CLK_DIV_ACP_VAL	0x12
-
-/* CLK_SRC_TOP0 */
-#define MUX_ACLK_300_GSCL_SEL		0x1
-#define MUX_ACLK_300_GSCL_MID_SEL	0x0
-#define MUX_ACLK_400_SEL		0x0
-#define MUX_ACLK_333_SEL		0x0
-#define MUX_ACLK_300_DISP1_SEL		0x1
-#define MUX_ACLK_300_DISP1_MID_SEL	0x0
-#define MUX_ACLK_200_SEL		0x0
-#define MUX_ACLK_166_SEL		0x0
-#define CLK_SRC_TOP0_VAL	((MUX_ACLK_300_GSCL_SEL << 25) \
-				| (MUX_ACLK_300_GSCL_MID_SEL << 24) \
-				| (MUX_ACLK_400_SEL << 20) \
-				| (MUX_ACLK_333_SEL << 16) \
-				| (MUX_ACLK_300_DISP1_SEL << 15) \
+/* CLK_SRC_TOP0	*/
+#define MUX_ACLK_300_GSCL_SEL           0x0
+#define MUX_ACLK_300_GSCL_MID_SEL       0x0
+#define MUX_ACLK_400_G3D_MID_SEL        0x0
+#define MUX_ACLK_333_SEL	        0x0
+#define MUX_ACLK_300_DISP1_SEL	        0x0
+#define MUX_ACLK_300_DISP1_MID_SEL      0x0
+#define MUX_ACLK_200_SEL	        0x0
+#define MUX_ACLK_166_SEL	        0x0
+#define CLK_SRC_TOP0_VAL	((MUX_ACLK_300_GSCL_SEL  << 25)		\
+				| (MUX_ACLK_300_GSCL_MID_SEL << 24)	\
+				| (MUX_ACLK_400_G3D_MID_SEL << 20)	\
+				| (MUX_ACLK_333_SEL << 16)		\
+				| (MUX_ACLK_300_DISP1_SEL << 15)	\
    			| (MUX_ACLK_300_DISP1_MID_SEL << 14)	\
-				| (MUX_ACLK_200_SEL << 12) \
+				| (MUX_ACLK_200_SEL << 12)		\
    			| (MUX_ACLK_166_SEL << 8))
-/* CLK_SRC_TOP1 */
-#define MUX_ACLK_400_ISP_SEL		0x0
-#define MUX_ACLK_400_IOP_SEL		0x0
-#define MUX_ACLK_MIPI_HSI_TXBASE_SEL	0x0
-#define CLK_SRC_TOP1_VAL		((MUX_ACLK_400_ISP_SEL << 24) \
-					|(MUX_ACLK_400_IOP_SEL << 20) \
-					|(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16))
+/* CLK_SRC_TOP1	*/
+#define MUX_ACLK_400_G3D_SEL            0x1
+#define MUX_ACLK_400_ISP_SEL            0x0
+#define MUX_ACLK_400_IOP_SEL            0x0
+#define MUX_ACLK_MIPI_HSI_TXBASE_SEL    0x0
+#define MUX_ACLK_300_GSCL_MID1_SEL      0x0
+#define MUX_ACLK_300_DISP1_MID1_SEL     0x0
+#define CLK_SRC_TOP1_VAL	((MUX_ACLK_400_G3D_SEL << 28)           \
+				|(MUX_ACLK_400_ISP_SEL << 24)           \
+				|(MUX_ACLK_400_IOP_SEL << 20)           \
+				|(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16)   \
+				|(MUX_ACLK_300_GSCL_MID1_SEL << 12)     \
+				|(MUX_ACLK_300_DISP1_MID1_SEL << 8))
/* CLK_SRC_TOP2 */
-#define MUX_BPLL_USER_SEL	0x1
-#define MUX_MPLL_USER_SEL	0x1
-#define MUX_VPLL_SEL		0x0
-#define MUX_EPLL_SEL		0x0
-#define MUX_CPLL_SEL		0x0
-#define VPLLSRC_SEL		0x0
-#define CLK_SRC_TOP2_VAL	((MUX_BPLL_USER_SEL << 24) \
-				| (MUX_MPLL_USER_SEL << 20) \
-				| (MUX_VPLL_SEL << 16) \
-				| (MUX_EPLL_SEL << 12) \
-				| (MUX_CPLL_SEL << 8) \
+#define MUX_GPLL_SEL                    0x1
+#define MUX_BPLL_USER_SEL               0x0
+#define MUX_MPLL_USER_SEL               0x0
+#define MUX_VPLL_SEL                    0x1
+#define MUX_EPLL_SEL                    0x1
+#define MUX_CPLL_SEL                    0x1
+#define VPLLSRC_SEL                     0x0
+#define CLK_SRC_TOP2_VAL	((MUX_GPLL_SEL << 28)		\
+				| (MUX_BPLL_USER_SEL << 24)	\
+				| (MUX_MPLL_USER_SEL << 20)	\
+				| (MUX_VPLL_SEL << 16)	        \
+				| (MUX_EPLL_SEL << 12)	        \
+				| (MUX_CPLL_SEL << 8)           \
    			| (VPLLSRC_SEL))
 /* CLK_SRC_TOP3 */
-#define MUX_ACLK_333_SUB_SEL		0x1
-#define MUX_ACLK_400_SUB_SEL		0x1
-#define MUX_ACLK_266_ISP_SUB_SEL	0x1
-#define MUX_ACLK_266_GPS_SUB_SEL	0x1
-#define MUX_ACLK_300_GSCL_SUB_SEL	0x1
-#define MUX_ACLK_266_GSCL_SUB_SEL	0x1
-#define MUX_ACLK_300_DISP1_SUB_SEL	0x1
-#define MUX_ACLK_200_DISP1_SUB_SEL	0x1
-#define CLK_SRC_TOP3_VAL		((MUX_ACLK_333_SUB_SEL << 24) \
-					| (MUX_ACLK_400_SUB_SEL << 20) \
-					| (MUX_ACLK_266_ISP_SUB_SEL << 16) \
-					| (MUX_ACLK_266_GPS_SUB_SEL << 12) \
-					| (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
-					| (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
-					| (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
-					| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
-
-/* CLK_DIV_TOP0 */
-#define ACLK_300_RATIO		0x0
-#define ACLK_400_RATIO		0x3
-#define ACLK_333_RATIO		0x2
+#define MUX_ACLK_333_SUB_SEL            0x1
+#define MUX_ACLK_400_SUB_SEL            0x1
+#define MUX_ACLK_266_ISP_SUB_SEL        0x1
+#define MUX_ACLK_266_GPS_SUB_SEL        0x0
+#define MUX_ACLK_300_GSCL_SUB_SEL       0x1
+#define MUX_ACLK_266_GSCL_SUB_SEL       0x1
+#define MUX_ACLK_300_DISP1_SUB_SEL      0x1
+#define MUX_ACLK_200_DISP1_SUB_SEL      0x1
+#define CLK_SRC_TOP3_VAL	((MUX_ACLK_333_SUB_SEL << 24)	        \
+				| (MUX_ACLK_400_SUB_SEL << 20)	        \
+				| (MUX_ACLK_266_ISP_SUB_SEL << 16)	\
+				| (MUX_ACLK_266_GPS_SUB_SEL << 12)      \
+				| (MUX_ACLK_300_GSCL_SUB_SEL << 10)     \
+				| (MUX_ACLK_266_GSCL_SUB_SEL << 8)      \
+				| (MUX_ACLK_300_DISP1_SUB_SEL << 6)     \
+				| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
+
+/* CLK_DIV_TOP0	*/
+#define ACLK_300_DISP1_RATIO	0x2
+#define ACLK_400_G3D_RATIO	0x0
+#define ACLK_333_RATIO		0x0
 #define ACLK_266_RATIO		0x2
 #define ACLK_200_RATIO		0x3
-#define ACLK_166_RATIO		0x5
+#define ACLK_166_RATIO		0x1
 #define ACLK_133_RATIO		0x1
 #define ACLK_66_RATIO		0x5
-#define CLK_DIV_TOP0_VAL	((ACLK_300_RATIO << 28) \
-				| (ACLK_400_RATIO << 24) \
-				| (ACLK_333_RATIO << 20) \
-				| (ACLK_266_RATIO << 16) \
-				| (ACLK_200_RATIO << 12) \
-				| (ACLK_166_RATIO << 8) \
-				| (ACLK_133_RATIO << 4) \
+
+#define CLK_DIV_TOP0_VAL	((ACLK_300_DISP1_RATIO << 28)	\
+				| (ACLK_400_G3D_RATIO << 24)	\
+				| (ACLK_333_RATIO  << 20)	\
+				| (ACLK_266_RATIO << 16)	\
+				| (ACLK_200_RATIO << 12)	\
+				| (ACLK_166_RATIO << 8)		\
+				| (ACLK_133_RATIO << 4)		\
    			| (ACLK_66_RATIO))
-/* CLK_DIV_TOP1 */
-#define ACLK_MIPI_HSI_TX_BASE_RATIO	0x3
-#define ACLK_66_PRE_RATIO	0x1
-#define ACLK_400_ISP_RATIO	0x1
-#define ACLK_400_IOP_RATIO	0x1
-#define ACLK_300_GSCL_RATIO	0x0
-#define ACLK_266_GPS_RATIO	0x7
-
-#define CLK_DIV_TOP1_VAL	((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
-				| (ACLK_66_PRE_RATIO << 24) \
-				| (ACLK_400_ISP_RATIO << 20) \
-				| (ACLK_400_IOP_RATIO << 16) \
-				| (ACLK_300_GSCL_RATIO << 12) \
-				| (ACLK_266_GPS_RATIO << 8))
-
-/* APLL_LOCK */
-#define APLL_LOCK_VAL		(0x3E8)
-/* MPLL_LOCK */
-#define MPLL_LOCK_VAL		(0x2F1)
-/* CPLL_LOCK */
-#define CPLL_LOCK_VAL		(0x3E8)
-/* EPLL_LOCK */
-#define EPLL_LOCK_VAL		(0x2321)
-/* VPLL_LOCK */
-#define VPLL_LOCK_VAL		(0x2321)
-/* BPLL_LOCK */
-#define BPLL_LOCK_VAL		(0x3E8)
+/* CLK_DIV_TOP1	*/
+#define ACLK_MIPI_HSI_TX_BASE_RATIO     0x3
+#define ACLK_66_PRE_RATIO               0x1
+#define ACLK_400_ISP_RATIO              0x1
+#define ACLK_400_IOP_RATIO              0x1
+#define ACLK_300_GSCL_RATIO             0x2
+
+#define CLK_DIV_TOP1_VAL	((ACLK_MIPI_HSI_TX_BASE_RATIO << 28)	\
+				| (ACLK_66_PRE_RATIO << 24)		\
+				| (ACLK_400_ISP_RATIO  << 20)		\
+				| (ACLK_400_IOP_RATIO << 16)		\
+				| (ACLK_300_GSCL_RATIO << 12))
+
+/* APLL_LOCK	*/
+#define APLL_LOCK_VAL	(0x546)
+/* MPLL_LOCK	*/
+#define MPLL_LOCK_VAL	(0x546)
+/* CPLL_LOCK	*/
+#define CPLL_LOCK_VAL	(0x546)
+/* GPLL_LOCK	*/
+#define GPLL_LOCK_VAL	(0x546)
+/* EPLL_LOCK	*/
+#define EPLL_LOCK_VAL	(0x3A98)
+/* VPLL_LOCK	*/
+#define VPLL_LOCK_VAL	(0x3A98)
+/* BPLL_LOCK	*/
+#define BPLL_LOCK_VAL	(0x546)
+
+#define MUX_APLL_SEL_MASK	(1 << 0)
+#define MUX_MPLL_SEL_MASK	(1 << 8)
+#define MPLL_SEL_MOUT_MPLLFOUT	(2 << 8)
+#define MUX_CPLL_SEL_MASK	(1 << 8)
+#define MUX_EPLL_SEL_MASK	(1 << 12)
+#define MUX_VPLL_SEL_MASK	(1 << 16)
+#define MUX_GPLL_SEL_MASK	(1 << 28)
+#define MUX_BPLL_SEL_MASK	(1 << 0)
+#define MUX_HPM_SEL_MASK	(1 << 20)
+#define HPM_SEL_SCLK_MPLL	(1 << 21)
+#define APLL_CON0_LOCKED	(1 << 29)
+#define MPLL_CON0_LOCKED	(1 << 29)
+#define BPLL_CON0_LOCKED	(1 << 29)
+#define CPLL_CON0_LOCKED	(1 << 29)
+#define EPLL_CON0_LOCKED	(1 << 29)
+#define GPLL_CON0_LOCKED	(1 << 29)
+#define VPLL_CON0_LOCKED	(1 << 29)
+#define CLK_REG_DISABLE		0x0
+#define TOP2_VAL		0x0110000
/* CLK_SRC_PERIC0 */
+#define PWM_SEL		0
+#define UART3_SEL	6
+#define UART2_SEL	6
+#define UART1_SEL	6
+#define UART0_SEL	6
+/* SRC_CLOCK = SCLK_MPLL */
+#define CLK_SRC_PERIC0_VAL	((PWM_SEL << 24)        \
+				| (UART3_SEL << 12)     \
+				| (UART2_SEL << 8)       \
+				| (UART1_SEL << 4)      \
+				| (UART0_SEL))
+
+/* CLK_SRC_PERIC1 */
 /* SRC_CLOCK = SCLK_MPLL */
-#define PWM_SEL			0
-#define UART4_SEL		6
-#define UART3_SEL		6
-#define UART2_SEL		6
-#define UART1_SEL		6
-#define UART0_SEL		6
-#define CLK_SRC_PERIC0_VAL	((PWM_SEL << 24) \
-				| (UART4_SEL << 16) \
-				| (UART3_SEL << 12) \
-				| (UART2_SEL << 8) \
-				| (UART1_SEL << 4) \
-				| (UART0_SEL << 0))
-
-#define CLK_SRC_FSYS_VAL	0x66666
-#define CLK_DIV_FSYS0_VAL	0x0BB00000
-#define CLK_DIV_FSYS1_VAL	0x000f000f
-#define CLK_DIV_FSYS2_VAL	0x020f020f
-#define CLK_DIV_FSYS3_VAL	0x000f
-
-/* CLK_DIV_PERIC0 */
-#define UART5_RATIO		8
-#define UART4_RATIO		8
-#define UART3_RATIO		8
-#define UART2_RATIO		8
-#define UART1_RATIO		8
-#define UART0_RATIO		8
-#define CLK_DIV_PERIC0_VAL	((UART4_RATIO << 16) \
-				| (UART3_RATIO << 12) \
-				| (UART2_RATIO << 8) \
-				| (UART1_RATIO << 4) \
-				| (UART0_RATIO << 0))
-
-/* CLK_DIV_PERIC3 */
-#define PWM_RATIO		8
-#define CLK_DIV_PERIC3_VAL	(PWM_RATIO << 0)
+#define SPI0_SEL		6
+#define SPI1_SEL		6
+#define SPI2_SEL		6
+#define CLK_SRC_PERIC1_VAL	((SPI2_SEL << 24) \
+				| (SPI1_SEL << 20) \
+				| (SPI0_SEL << 16))
+
+/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
+#define SPI0_ISP_SEL		6
+#define SPI1_ISP_SEL		6
+#define SCLK_SRC_ISP_VAL	(SPI1_ISP_SEL << 4) \
+				| (SPI0_ISP_SEL << 0)
+
+/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
+#define SPI0_ISP_RATIO		0xf
+#define SPI1_ISP_RATIO		0xf
+#define SCLK_DIV_ISP_VAL	(SPI1_ISP_RATIO << 12) \
+				| (SPI0_ISP_RATIO << 0)
+
+/* CLK_DIV_PERIL0	*/
+#define UART5_RATIO	7
+#define UART4_RATIO	7
+#define UART3_RATIO	7
+#define UART2_RATIO	7
+#define UART1_RATIO	7
+#define UART0_RATIO	7
+
+#define CLK_DIV_PERIC0_VAL	((UART3_RATIO << 12)    \
+				| (UART2_RATIO << 8)    \
+				| (UART1_RATIO << 4)    \
+				| (UART0_RATIO))
+/* CLK_DIV_PERIC1 */
+#define SPI1_RATIO		0x7
+#define SPI0_RATIO		0xf
+#define SPI1_SUB_RATIO		0x0
+#define SPI0_SUB_RATIO		0x0
+#define CLK_DIV_PERIC1_VAL	((SPI1_SUB_RATIO << 24) \
+				| ((SPI1_RATIO << 16) \
+				| (SPI0_SUB_RATIO << 8) \
+				| (SPI0_RATIO << 0)))
+
+/* CLK_DIV_PERIC2 */
+#define SPI2_RATIO		0xf
+#define SPI2_SUB_RATIO		0x0
+#define CLK_DIV_PERIC2_VAL	((SPI2_SUB_RATIO << 8) \
+				| (SPI2_RATIO << 0))
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO_MASK		0xf
+#define MMC2_RATIO_VAL		0x3
+#define MMC2_RATIO_OFFSET	0
+
+#define MMC2_PRE_RATIO_MASK	0xff
+#define MMC2_PRE_RATIO_VAL	0x9
+#define MMC2_PRE_RATIO_OFFSET	8
+
+#define MMC3_RATIO_MASK		0xf
+#define MMC3_RATIO_VAL		0x1
+#define MMC3_RATIO_OFFSET	16
+
+#define MMC3_PRE_RATIO_MASK	0xff
+#define MMC3_PRE_RATIO_VAL	0x0
+#define MMC3_PRE_RATIO_OFFSET	24
/* CLK_SRC_LEX */
-#define CLK_SRC_LEX_VAL		0x0
+#define CLK_SRC_LEX_VAL         0x0
/* CLK_DIV_LEX */
-#define CLK_DIV_LEX_VAL		0x10
+#define CLK_DIV_LEX_VAL         0x10
/* CLK_DIV_R0X */
-#define CLK_DIV_R0X_VAL		0x10
+#define CLK_DIV_R0X_VAL         0x10
/* CLK_DIV_L0X */
-#define CLK_DIV_R1X_VAL		0x10
+#define CLK_DIV_R1X_VAL         0x10
-/* SCLK_SRC_ISP */
-#define SCLK_SRC_ISP_VAL	0x600
 /* CLK_DIV_ISP0 */
-#define CLK_DIV_ISP0_VAL	0x31
+#define CLK_DIV_ISP0_VAL        0x31
/* CLK_DIV_ISP1 */
-#define CLK_DIV_ISP1_VAL	0x0
+#define CLK_DIV_ISP1_VAL        0x0
/* CLK_DIV_ISP2 */
-#define CLK_DIV_ISP2_VAL	0x1
+#define CLK_DIV_ISP2_VAL        0x1
-#define MPLL_DEC	(MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1)))
+/* CLK_SRC_DISP1_0 */
+#define CLK_SRC_DISP1_0_VAL	0x6
+
+/*
+ * DIV_DISP1_0
+ * For DP, divisor should be 2
+ */
+#define CLK_DIV_DISP1_0_FIMD1	(2 << 0)
+
+/* CLK_GATE_IP_DISP1 */
+#define CLK_GATE_DP1_ALLOW	(1 << 4)
/*
  * TZPC Register Value :
@@ -347,103 +464,66 @@
  */
 #define DECPROTXSET		0xFF
-/* DMC Init */
-#define SET			1
-#define RESET			0
-/* (Memory Interleaving Size = 1 << IV_SIZE) */
-#define CONFIG_IV_SIZE		0x07
+#define DDR3PHY_CTRL_PHY_RESET	(1 << 0)
+#define DDR3PHY_CTRL_PHY_RESET_OFF	(0 << 0)
+
+#define PHY_CON0_RESET_VAL	0x17020a40
+#define P0_CMD_EN		(1 << 14)
+#define BYTE_RDLVL_EN		(1 << 13)
+#define CTRL_SHGATE		(1 << 8)
+
+#define PHY_CON1_RESET_VAL	0x09210100
+#define CTRL_GATEDURADJ_MASK	(0xf << 20)
-#define PHY_RESET_VAL	(0 << 0)
+#define PHY_CON2_RESET_VAL	0x00010004
+#define INIT_DESKEW_EN		(1 << 6)
+#define RDLVL_GATE_EN		(1 << 24)
/*ZQ Configurations */
 #define PHY_CON16_RESET_VAL	0x08000304
-#define ZQ_MODE_DDS_VAL		(0x5 << 24)
-#define ZQ_MODE_TERM_VAL	(0x5 << 21)
-#define SET_ZQ_MODE_DDS_VAL(x)	(x = (x & ~(0x7 << 24)) | ZQ_MODE_DDS_VAL)
-#define SET_ZQ_MODE_TERM_VAL(x)	(x = (x & ~(0x7 << 21)) | ZQ_MODE_TERM_VAL)
-
-#define ZQ_MODE_NOTERM		(1 << 19)
 #define ZQ_CLK_DIV_EN		(1 << 18)
 #define ZQ_MANUAL_STR		(1 << 1)
+#define ZQ_DONE			(1 << 0)
+
+#define CTRL_RDLVL_GATE_ENABLE	1
+#define CTRL_RDLVL_GATE_DISABLE	1
+
+/* Direct Command */
+#define DIRECT_CMD_NOP			0x07000000
+#define DIRECT_CMD_PALL			0x01000000
+#define DIRECT_CMD_ZQINIT		0x0a000000
+#define DIRECT_CMD_CHANNEL_SHIFT	28
+#define DIRECT_CMD_CHIP_SHIFT		20
+
+/* DMC PHY Control0 register */
+#define PHY_CONTROL0_RESET_VAL	0x0
+#define MEM_TERM_EN	(1 << 31)	/* Termination enable for memory */
+#define PHY_TERM_EN	(1 << 30)	/* Termination enable for PHY */
+#define DMC_CTRL_SHGATE	(1 << 29)	/* Duration of DQS gating signal */
+#define FP_RSYNC	(1 << 3)	/* Force DLL resyncronization */
+
+/* Driver strength for CK, CKE, CS & CA */
+#define IMP_OUTPUT_DRV_40_OHM	0x5
+#define IMP_OUTPUT_DRV_30_OHM	0x7
+#define CA_CK_DRVR_DS_OFFSET	9
+#define CA_CKE_DRVR_DS_OFFSET	6
+#define CA_CS_DRVR_DS_OFFSET	3
+#define CA_ADR_DRVR_DS_OFFSET	0
+
+#define PHY_CON42_CTRL_BSTLEN_SHIFT	8
+#define PHY_CON42_CTRL_RDLAT_SHIFT	0
+
+struct mem_timings;
+
+/* Errors that we can encourter in low-level setup */
+enum {
+	SETUP_ERR_OK,
+	SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
+	SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
+};
-/* Channel and Chip Selection */
-#define CONFIG_DMC_CHANNELS		2
-#define CONFIG_CHIPS_PER_CHANNEL	2
-
-#define SET_CMD_CHANNEL(x, y)	(x = (x & ~(1 << 28)) | y << 28)
-#define SET_CMD_CHIP(x, y)	(x = (x & ~(1 << 20)) | y << 20)
-
-/* Diret Command */
-#define	DIRECT_CMD_NOP		0x07000000
-#define DIRECT_CMD_MRS1		0x00071C00
-#define DIRECT_CMD_MRS2		0x00010BFC
-#define DIRECT_CMD_MRS3		0x00000708
-#define DIRECT_CMD_MRS4		0x00000818
-#define	DIRECT_CMD_PALL		0x01000000
-
-/* DLL Resync */
-#define FP_RSYNC		(1 << 3)
-
-#define CONFIG_CTRL_DLL_ON(x, y)	(x = (x & ~(1 << 5)) | y << 5)
-#define CONFIG_CTRL_START(x, y)		(x = (x & ~(1 << 6)) | y << 6)
-#define SET_CTRL_FORCE_VAL(x, y)	(x = (x & ~(0x7F << 8)) | y << 8)
-
-/* RDLVL */
-#define PHY_CON0_RESET_VAL	0x17023240
-#define DDR_MODE_LPDDR2		0x2
-#define BYTE_RDLVL_EN		(1 << 13)
-#define CTRL_ATGATE		(1 << 6)
-#define SET_CTRL_DDR_MODE(x, y)	(x = (x & ~(0x3 << 11)) | y << 11)
-
-#define PHY_CON1_RESET_VAL	0x9210100
-#define RDLVL_RDDATAPADJ	0x1
-#define SET_RDLVL_RDDATAPADJ	((PHY_CON1_RESET_VAL & ~(0xFFFF << 0))\
-					| RDLVL_RDDATAPADJ << 0)
-#define PHY_CON2_RESET_VAL	0x00010004
-#define RDLVL_EN		(1 << 25)
-#define RDDSKEW_CLEAR		(1 << 13)
-
-#define CTRL_RDLVL_DATA_EN	(1 << 1)
-#define LPDDR2_ADDR		0x00000208
-
-#define DMC_MEMCONFIG0_VAL	0x00001323
-#define DMC_MEMCONFIG1_VAL	0x00001323
-#define DMC_MEMBASECONFIG0_VAL	0x00400780
-#define DMC_MEMBASECONFIG1_VAL	0x00800780
-#define DMC_MEMCONTROL_VAL	0x00212500
-#define DMC_PRECHCONFIG_VAL		0xFF000000
-#define DMC_PWRDNCONFIG_VAL		0xFFFF00FF
-#define DMC_TIMINGREF_VAL		0x0000005D
-#define DMC_TIMINGROW_VAL		0x2336544C
-#define DMC_TIMINGDATA_VAL		0x24202408
-#define DMC_TIMINGPOWER_VAL		0x38260235
-
-#define CTRL_BSTLEN		0x04
-#define CTRL_RDLAT		0x08
-#define PHY_CON42_VAL		(CTRL_BSTLEN << 8 | CTRL_RDLAT << 0)
-
-/* DQS, DQ, DEBUG offsets */
-#define	SET_DQS_OFFSET_VAL	0x7F7F7F7F
-#define	SET_DQ_OFFSET_VAL	0x7F7F7F7F
-#define	SET_DEBUG_OFFSET_VAL	0x7F
-
-#define	RESET_DQS_OFFSET_VAL	0x08080808
-#define	RESET_DQ_OFFSET_VAL	0x08080808
-#define	RESET_DEBUG_OFFSET_VAL	0x8
-
-#define CTRL_PULLD_DQ		(0x0F << 8)
-#define CTRL_PULLD_DQS		(0x0F << 0)
-
-#define DFI_INIT_START		(1 << 28)
-
-#define CLK_STOP_EN	(1 << 0)
-#define DPWRDN_EN	(1 << 1)
-#define DSREF_EN	(1 << 5)
-
-#define AREF_EN			(1 << 5)
-void sdelay(unsigned long);
 void mem_ctrl_init(void);
 void system_clock_init(void);
 void tzpc_init(void);
-- 
1.7.4.4


    