DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all.
The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all.
So, handle the phy masking bits accordingly on respective interface type cases.
Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko andy.shevchenko@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/usb/dwc3/core.c | 12 ++++++++---- drivers/usb/dwc3/core.h | 20 ++++++++------------ 2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 0f9a632816..77c555e769 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -622,15 +622,19 @@ static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
/* Set dwc3 usb2 phy config */ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - reg |= DWC3_GUSB2PHYCFG_PHYIF; - reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
switch (hsphy_mode) { case USBPHY_INTERFACE_MODE_UTMI: - reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; + reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | + DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); + reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); break; case USBPHY_INTERFACE_MODE_UTMIW: - reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; + reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | + DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); + reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); break; default: break; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index bff53e072b..1c08a2c5b6 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -162,18 +162,14 @@ /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) -#define DWC3_GUSB2PHYCFG_PHYIF BIT(3) - -/* Global USB2 PHY Configuration Mask */ -#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10) - -/* Global USB2 PHY Configuration Offset */ -#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10 - -#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \ - DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) -#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \ - DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define USBTRDTIM_UTMI_8_BIT 9 +#define USBTRDTIM_UTMI_16_BIT 5 +#define UTMI_PHYIF_16_BIT 1 +#define UTMI_PHYIF_8_BIT 0
/* Global USB3 PIPE Control Register */ #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)