Dear C Nauman,
I'm sorry to late review.
On 27 August 2010 00:43, C Nauman cnauman@diagraph.com wrote:
This patch adds generic support for the Samsung s3c2440 processor.
Global s3c24x0 changes to struct members converting from upper case to to lower case.
Signed-off-by: Craig Nauman cnauman@diagraph.com Cc: kevin.morfitt@fearnside-systems.co.uk
- v3 Fixup style problems checkpatch.pl yields one error from David's name
- v2 Fix global s3c24x0 struct members to lower case as requested by Minkyu
- v1 Start from patch posted by Kevin Morfitt 2009-06-19
arch/arm/cpu/arm920t/s3c24x0/speed.c | 31 +- arch/arm/cpu/arm920t/s3c24x0/timer.c | 23 +- arch/arm/cpu/arm920t/s3c24x0/usb.c | 10 +- arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c | 12 +- arch/arm/include/asm/arch-s3c24x0/s3c2440.h | 163 ++++++ arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 672 +++++++++++++---------- arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h | 2 + board/mpl/vcma9/vcma9.c | 41 +- board/samsung/smdk2400/smdk2400.c | 28 +- board/samsung/smdk2410/smdk2410.c | 36 +- board/sbc2410x/sbc2410x.c | 44 +- board/trab/cmd_trab.c | 28 +- board/trab/rs485.c | 40 +- board/trab/trab.c | 67 ++-- board/trab/trab_fkt.c | 142 +++--- board/trab/tsc2000.c | 39 +- board/trab/tsc2000.h | 86 ++-- board/trab/vfd.c | 90 ++-- drivers/i2c/s3c24x0_i2c.c | 102 ++-- drivers/mtd/nand/s3c2410_nand.c | 25 +- drivers/rtc/s3c24x0_rtc.c | 52 +- drivers/serial/serial_s3c24x0.c | 26 +- 22 files changed, 1019 insertions(+), 740 deletions(-) create mode 100644 arch/arm/include/asm/arch-s3c24x0/s3c2440.h
diff --git a/arch/arm/cpu/arm920t/s3c24x0/speed.c b/arch/arm/cpu/arm920t/s3c24x0/speed.c index b13283a..c3e40d4 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/speed.c +++ b/arch/arm/cpu/arm920t/s3c24x0/speed.c @@ -54,9 +54,9 @@ static ulong get_PLLCLK(int pllreg) ulong r, m, p, s;
if (pllreg == MPLL)
- r = readl(&clk_power->MPLLCON);
- r = readl(&clk_power->mpllcon);
else if (pllreg == UPLL)
- r = readl(&clk_power->UPLLCON);
- r = readl(&clk_power->upllcon);
else hang();
@@ -64,7 +64,13 @@ static ulong get_PLLCLK(int pllreg) p = ((r & 0x003F0) >> 4) + 2; s = r & 0x3;
+#if defined(CONFIG_S3C2440)
- if (pllreg == MPLL)
- return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
- else
maybe this else is not necessary
+#endif return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
}
/* return FCLK frequency */ @@ -77,8 +83,23 @@ ulong get_FCLK(void) ulong get_HCLK(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 :
get_FCLK(); +#ifdef CONFIG_S3C2440
- switch (readl(&clk_power->clkdivn) & 0x6) {
- default:
- case 0:
- return get_FCLK();
- case 2:
- return get_FCLK() / 2;
- case 4:
- return (readl(&clk_power->camdivn) & (1 << 9)) ?
- get_FCLK() / 8 : get_FCLK() / 4;
- case 6:
- return (readl(&clk_power->camdivn) & (1 << 8)) ?
- get_FCLK() / 6 : get_FCLK() / 3;
- }
+#else
- return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 :
get_FCLK(); +#endif }
/* return PCLK frequency */ @@ -86,7 +107,7 @@ ulong get_PCLK(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 :
get_HCLK();
- return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 :
get_HCLK(); }
/* return UCLK frequency */ diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c index 7d47354..1512f12 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/timer.c +++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c @@ -43,7 +43,7 @@ static inline ulong READ_TIMER(void) { struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
- return readl(&timers->TCNTO4) & 0xffff;
- return readl(&timers->tcnto4) & 0xffff;
}
static ulong timestamp; @@ -56,7 +56,7 @@ int timer_init(void)
/* use PWM Timer 4 because it has no output */ /* prescaler for Timer 4 is 16 */
- writel(0x0f00, &timers->TCFG0);
- writel(0x0f00, &timers->tcfg0);
if (timer_load_val == 0) { /* * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 @@ -68,13 +68,13 @@ int timer_init(void) } /* load value for 10 ms timeout */ lastdec = timer_load_val;
- writel(timer_load_val, &timers->TCNTB4);
- /* auto load, manual update of Timer 4 */
- tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
- writel(tmr, &timers->TCON);
- /* auto load, start Timer 4 */
- writel(timer_load_val, &timers->tcntb4);
- /* auto load, manual update of timer 4 */
- tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
- writel(tmr, &timers->tcon);
- /* auto load, start timer 4 */
tmr = (tmr & ~0x0700000) | 0x0500000;
- writel(tmr, &timers->TCON);
- writel(tmr, &timers->tcon);
timestamp = 0;
return (0); @@ -181,6 +181,7 @@ ulong get_tbclk(void) tbclk = timer_load_val * 100; #elif defined(CONFIG_SBC2410X) || \ defined(CONFIG_SMDK2410) || \
- defined(CONFIG_S3C2440) || \
please tab instead of space.
defined(CONFIG_VCMA9) tbclk = CONFIG_SYS_HZ; #else @@ -206,13 +207,13 @@ void reset_cpu(ulong ignored) watchdog = s3c24x0_get_base_watchdog();
/* Disable watchdog */
- writel(0x0000, &watchdog->WTCON);
- writel(0x0000, &watchdog->wtcon);
/* Initialize watchdog timer count register */
- writel(0x0001, &watchdog->WTCNT);
- writel(0x0001, &watchdog->wtcnt);
/* Enable watchdog timer; assert reset at timer timeout */
- writel(0x0021, &watchdog->WTCON);
- writel(0x0021, &watchdog->wtcon);
while (1) /* loop forever and wait for reset to happen */; diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb.c b/arch/arm/cpu/arm920t/s3c24x0/usb.c index e468ed0..226a3f6 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/usb.c +++ b/arch/arm/cpu/arm920t/s3c24x0/usb.c @@ -39,14 +39,14 @@ int usb_cpu_init(void) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */
- writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
- writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
/* 1 = use pads related USB for USB host */
- writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
- writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
/* * Enable USB host clock. */
- writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
- writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
return 0; } @@ -55,14 +55,14 @@ int usb_cpu_stop(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); /* may not want to do this */
- writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
- writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
return 0; }
int usb_cpu_init_fail(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
- writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
return 0; }
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c index 5aa8d64..ccc9738 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c @@ -1666,13 +1666,13 @@ int usb_lowlevel_init(void) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */
- clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
- gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
- clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
- gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */
/* * Enable USB host clock. */
- clk_power->CLKCON |= (1 << 4);
- clk_power->clkcon |= (1 << 4);
memset(&gohci, 0, sizeof(struct ohci)); memset(&urb_priv, 0, sizeof(struct urb_priv)); @@ -1709,7 +1709,7 @@ int usb_lowlevel_init(void) if (hc_reset(&gohci) < 0) { hc_release_ohci(&gohci); /* Initialization failed */
- clk_power->CLKCON &= ~(1 << 4);
- clk_power->clkcon &= ~(1 << 4);
return -1; }
@@ -1722,7 +1722,7 @@ int usb_lowlevel_init(void) err("can't start usb-%s", gohci.slot_name); hc_release_ohci(&gohci); /* Initialization failed */
- clk_power->CLKCON &= ~(1 << 4);
- clk_power->clkcon &= ~(1 << 4);
return -1; } #ifdef DEBUG @@ -1748,7 +1748,7 @@ int usb_lowlevel_stop(void) /* call hc_release_ohci() here ? */ hc_reset(&gohci); /* may not want to do this */
- clk_power->CLKCON &= ~(1 << 4);
- clk_power->clkcon &= ~(1 << 4);
return 0; }
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h new file mode 100644 index 0000000..7e4518e --- /dev/null +++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h @@ -0,0 +1,163 @@ +/*
- (C) Copyright 2003
- David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+/************************************************
- NAME : s3c2440.h
- Version : 31.3.2003
- Based on S3C2440 User's manual Rev x.x
- ************************************************/
+#ifndef __S3C2440_H__ +#define __S3C2440_H__
+#define S3C24X0_UART_CHANNELS 3 +#define S3C24X0_SPI_CHANNELS 2
+/* S3C2440 only supports 512 Byte HW ECC */ +#define S3C2440_ECCSIZE 512 +#define S3C2440_ECCBYTES 3
+enum s3c24x0_uarts_nr {
- S3C24X0_UART0,
- S3C24X0_UART1,
- S3C24X0_UART2
+};
+/* S3C2440 device base addresses */ +#define S3C24X0_MEMCTL_BASE 0x48000000 +#define S3C24X0_USB_HOST_BASE 0x49000000 +#define S3C24X0_INTERRUPT_BASE 0x4A000000 +#define S3C24X0_DMA_BASE 0x4B000000 +#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 +#define S3C24X0_LCD_BASE 0x4D000000 +#define S3C2440_NAND_BASE 0x4E000000 +#define S3C24X0_UART_BASE 0x50000000 +#define S3C24X0_TIMER_BASE 0x51000000 +#define S3C24X0_USB_DEVICE_BASE 0x52000140 +#define S3C24X0_WATCHDOG_BASE 0x53000000 +#define S3C24X0_I2C_BASE 0x54000000 +#define S3C24X0_I2S_BASE 0x55000000 +#define S3C24X0_GPIO_BASE 0x56000000 +#define S3C24X0_RTC_BASE 0x57000000 +#define S3C2440_ADC_BASE 0x58000000 +#define S3C24X0_SPI_BASE 0x59000000 +#define S3C2440_SDI_BASE 0x5A000000
please remove this space
+/* include common stuff */ +#include <asm/arch/s3c24x0.h>
Ditto.
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) +{
- return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
+}
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) +{
- return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
+}
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) +{
- return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
+}
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) +{
- return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
+}
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) +{
- return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
+}
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) +{
- return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
+}
+static inline struct s3c2440_nand *s3c2440_get_base_nand(void) +{
- return (struct s3c2440_nand *)S3C2440_NAND_BASE;
+}
+static inline struct s3c24x0_uart
- *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
+{
- return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
+}
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) +{
- return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
+}
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) +{
- return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
+}
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) +{
- return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
+}
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) +{
- return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
+}
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) +{
- return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
+}
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) +{
- return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
+}
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) +{
- return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
+}
+static inline struct s3c2440_adc *s3c2440_get_base_adc(void) +{
- return (struct s3c2440_adc *)S3C2440_ADC_BASE;
+}
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) +{
- return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
+}
+static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void) +{
- return (struct s3c2440_sdi *)S3C2440_SDI_BASE;
+}
+#endif /*__S3C2440_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h index 15f53dd..f634d11 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h @@ -33,12 +33,12 @@
/* Memory controller (see manual chapter 5) */ struct s3c24x0_memctl {
- u32 BWSCON;
- u32 BANKCON[8];
- u32 REFRESH;
- u32 BANKSIZE;
- u32 MRSRB6;
- u32 MRSRB7;
- u32 bwscon;
- u32 bankcon[8];
- u32 refresh;
- u32 banksize;
- u32 mrsrb6;
- u32 mrsrb7;
};
Thanks Minkyu Kang