Hi Michal,
On Thu, Aug 16, 2012 at 1:30 AM, Michal Simek monstr@monstr.eu wrote:
Add support for Xilinx Zynq board.
Signed-off-by: Michal Simek monstr@monstr.eu
v2: Forget to also add config file
v3: Change name for serial driver Remove lowlevel_init from board folder Remove XPSS part from timer baseaddr Change name for Zynq gem driver Clean coding style Remove mac + ip addresses from config file Remove additional PHYs
board/xilinx/zynq/Makefile | 54 +++++++++++++++++++++ board/xilinx/zynq/board.c | 64 +++++++++++++++++++++++++ boards.cfg | 1 + include/configs/zynq.h | 110 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 229 insertions(+), 0 deletions(-) create mode 100644 board/xilinx/zynq/Makefile create mode 100644 board/xilinx/zynq/board.c create mode 100644 include/configs/zynq.h
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c new file mode 100644 index 0000000..4cb36f6 --- /dev/null +++ b/board/xilinx/zynq/board.c @@ -0,0 +1,64 @@ +/*
- (C) Copyright 2012 Michal Simek monstr@monstr.eu
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <netdev.h>
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void) +{
icache_enable();return 0;+}
+int board_late_init(void) +{
return 0;+}
+#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{
int ret = 0;+#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);+#endif
return ret;+} +#endif
+int dram_init(void) +{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;return 0;+}
+void reset_cpu(ulong addr) +{
while (1);+}
Why not explicitly reset, like Xilinx tree?
void reset_cpu(ulong addr) { /* unlock SLCR */ writel(XPSS_SLCR_UNLOCK_KEY, XPSS_SYS_CTRL_BASEADDR | XPSS_SLCR_UNLOCK); /* Tickle soft reset bit */ writel(1, XPSS_SYS_CTRL_BASEADDR | XPSS_SLCR_PSS_RST_CTRL);
while (1) ; }
diff --git a/include/configs/zynq.h b/include/configs/zynq.h new file mode 100644 index 0000000..8fb4f1b --- /dev/null +++ b/include/configs/zynq.h @@ -0,0 +1,110 @@ +/*
- (C) Copyright 2012 Michal Simek monstr@monstr.eu
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef __CONFIG_ZYNQ_H +#define __CONFIG_ZYNQ_H
+#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ +#define CONFIG_ZYNQ
+/* CPU clock */ +#define CONFIG_CPU_FREQ_HZ 800000000 +#define CONFIG_SYS_HZ 1000
+/* Ram */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
+/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}+#define CONFIG_BAUDRATE 115200
+/* XPSS Serial driver */ +#define CONFIG_ZYNQ_SERIAL +#define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000 +#define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE +#define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000
+/* SCU timer address is hardcoded */ +#define CONFIG_SCUTIMER_BASEADDR 0xF8F00600
+/* Ethernet driver */ +#define CONFIG_NET_MULTI +#define CONFIG_ZYNQ_GEM +#define CONFIG_ZYNQ_GEM_BASEADDR0 0xE000B000
+#define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_MAY_FAIL
+/* MII and Phylib */ +#define CONFIG_MII +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_PHYLIB +#define CONFIG_PHY_MARVELL
+/* Environment */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_MALLOC_LEN 0x400000 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \GENERATED_GBL_DATA_SIZE)+#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_LOAD_ADDR 0 +#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+/* OF */ +#define CONFIG_FIT +#define CONFIG_OF_LIBFDT
+/* Commands */ +#include <config_cmd_default.h>
+#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII
+#endif /* __CONFIG_ZYNQ_H */
1.7.0.4