From: Michael Trimarchi michael@amarulasolutions.com
Change the size create a glitch in the clken signal on second bank. According to the ddr manual the clken need to be sent accros the reset signal coming the cpu. The rank is calculated just before this function is called and the mctl_set_cr should not change this value anymore
Signed-off-by: Michael Trimarchi michael@amarulasolutions.com Signed-off-by: Shyam Saini shyam.saini@amarulasolutions.com --- Changelogs: V1->V2: Adjust commit description V2->V3: None --- arch/arm/mach-sunxi/dram_sun8i_a33.c | 3 --- 1 file changed, 3 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c index 5da01922bfaf..63e18f17d0db 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c @@ -45,14 +45,12 @@ static void mctl_set_cr(struct dram_para *para)
static void auto_detect_dram_size(struct dram_para *para) { - u8 orig_rank = para->rank; int rows, columns;
/* Row detect */ para->page_size = 512; para->seq = 1; para->rows = 16; - para->rank = 1; mctl_set_cr(para); for (rows = 11 ; rows < 16 ; rows++) { if (mctl_mem_matches(1 << (rows + 9))) /* row-column */ @@ -69,7 +67,6 @@ static void auto_detect_dram_size(struct dram_para *para) }
para->seq = 0; - para->rank = orig_rank; para->rows = rows; para->page_size = 1 << columns; mctl_set_cr(para);