dwmmc controller has default internal divider by 2, and we always provide double of the clock rate request by dwmmc controller. Sync code for all Rockchip SoC with: 4055b46 rockchip: clk: rk3288: fix mmc clock setting
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Changes in v2:
- add comment for mmc clock div 2 internal
- update the commit message
drivers/clk/rockchip/clk_rk3036.c | 6 +++--- drivers/clk/rockchip/clk_rk3188.c | 5 +++-- drivers/clk/rockchip/clk_rk322x.c | 8 ++++---- drivers/clk/rockchip/clk_rk3288.c | 1 + drivers/clk/rockchip/clk_rk3328.c | 9 +++++---- drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++---- 6 files changed, 24 insertions(+), 17 deletions(-)
Applied to u-boot-rockchip, thanks!