RISC-V U-Boot expects the hart ID to be passed to it via register a0 by the previous boot stage. Machine mode firmware such as BBL and OpenSBI do this when starting their payload (U-Boot) in supervisor mode. If U-Boot is running in machine mode, this task must be handled by the boot ROM. Explicitly populate register a0 with the hart ID from the mhartid CSR to avoid possible problems on RISC-V processors with a boot ROM that does not handle this task.
Suggested-by: Rick Chen rick@andestech.com Signed-off-by: Lukas Auer lukas.auer@aisec.fraunhofer.de Reviewed-by: Anup Patel anup.patel@wdc.com Reviewed-by: Atish Patra atish.patra@wdc.com Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Rick Chen rick@andestech.com Tested-by: Rick Chen rick@andestech.com ---
Changes in v3: None Changes in v2: - New patch to populate register a0 with the hart ID from the mhartid CSR in machine-mode
arch/riscv/cpu/start.S | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index f55b8cbc37..5ac899b141 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -36,6 +36,10 @@ .section .text .globl _start _start: +#ifdef CONFIG_RISCV_MMODE + csrr a0, mhartid +#endif + /* save hart id and dtb pointer */ mv tp, a0 mv s1, a1