This allows us to generate DCD table data appropriate for MX6Q, MX6DL, or MX6Solo simply by defining CONFIG_MX6Q, CONFIG_MX6DL, or CONFIG_MX6S
Signed-off-by: Troy Kisky troy.kisky@boundarydevices.com --- arch/arm/include/asm/arch-mx6/imx-mkimage.h | 156 ++++++++++++++++ board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 245 +++++++++++++------------- 2 files changed, 280 insertions(+), 121 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx6/imx-mkimage.h
diff --git a/arch/arm/include/asm/arch-mx6/imx-mkimage.h b/arch/arm/include/asm/arch-mx6/imx-mkimage.h new file mode 100644 index 0000000..4abd3f1 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/imx-mkimage.h @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2012 Boundary Devices Inc. + * + * Licensed under the GPL-2 or later. + */ +#ifndef __ASM_ARCH_IMX_MKIMAGE_H__ +#define __ASM_ARCH_IMX_MKIMAGE_H__ + +#define IOMUXC_GPR4 0x020e0010 +#define IOMUXC_GPR6 0x020e0018 +#define IOMUXC_GPR7 0x020e001c + +/* mx6 duallite and solo have same offsets */ + +#define IOM_DRAM_DQM0 MA(0x020e05ac, 0x020e0470, 0x0) +#define IOM_DRAM_DQM1 MA(0x020e05b4, 0x020e0474, 0x0) +#define IOM_DRAM_DQM2 MA(0x020e0528, 0x020e0478, 0x0) +#define IOM_DRAM_DQM3 MA(0x020e0520, 0x020e047c, 0x0) +#define IOM_DRAM_DQM4 MA(0x020e0514, 0x020e0480, 0x0) +#define IOM_DRAM_DQM5 MA(0x020e0510, 0x020e0484, 0x0) +#define IOM_DRAM_DQM6 MA(0x020e05bc, 0x020e0488, 0x0) +#define IOM_DRAM_DQM7 MA(0x020e05c4, 0x020e048c, 0x0) + +#define IOM_DRAM_CAS MA(0x020e056c, 0x020e0464, 0x0) +#define IOM_DRAM_RAS MA(0x020e0578, 0x020e0490, 0x0) +#define IOM_DRAM_RESET MA(0x020e057c, 0x020e0494, 0x0) +#define IOM_DRAM_SDCLK_0 MA(0x020e0588, 0x020e04ac, 0x0) +#define IOM_DRAM_SDCLK_1 MA(0x020e0594, 0x020e04b0, 0x0) +#define IOM_DRAM_SDBA2 MA(0x020e058c, 0x020e04a0, 0x0) +#define IOM_DRAM_SDCKE0 MA(0x020e0590, 0x020e04a4, 0x0) +#define IOM_DRAM_SDCKE1 MA(0x020e0598, 0x020e04a8, 0x0) +#define IOM_DRAM_SDODT0 MA(0x020e059c, 0x020e04b4, 0x0) +#define IOM_DRAM_SDODT1 MA(0x020e05a0, 0x020e04b8, 0x0) + +#define IOM_DRAM_SDQS0 MA(0x020e05a8, 0x020e04bc, 0x0) +#define IOM_DRAM_SDQS1 MA(0x020e05b0, 0x020e04c0, 0x0) +#define IOM_DRAM_SDQS2 MA(0x020e0524, 0x020e04c4, 0x0) +#define IOM_DRAM_SDQS3 MA(0x020e051c, 0x020e04c8, 0x0) +#define IOM_DRAM_SDQS4 MA(0x020e0518, 0x020e04cc, 0x0) +#define IOM_DRAM_SDQS5 MA(0x020e050c, 0x020e04d0, 0x0) +#define IOM_DRAM_SDQS6 MA(0x020e05b8, 0x020e04d4, 0x0) +#define IOM_DRAM_SDQS7 MA(0x020e05c0, 0x020e04d8, 0x0) + +#define IOM_GRP_B0DS MA(0x020e0784, 0x020e0764, 0x0) +#define IOM_GRP_B1DS MA(0x020e0788, 0x020e0770, 0x0) +#define IOM_GRP_B2DS MA(0x020e0794, 0x020e0778, 0x0) +#define IOM_GRP_B3DS MA(0x020e079c, 0x020e077c, 0x0) +#define IOM_GRP_B4DS MA(0x020e07a0, 0x020e0780, 0x0) +#define IOM_GRP_B5DS MA(0x020e07a4, 0x020e0784, 0x0) +#define IOM_GRP_B6DS MA(0x020e07a8, 0x020e078c, 0x0) +#define IOM_GRP_B7DS MA(0x020e0748, 0x020e0748, 0x0) +#define IOM_GRP_ADDDS MA(0x020e074c, 0x020e074c, 0x0) +#define IOM_DDRMODE_CTL MA(0x020e0750, 0x020e0750, 0x0) +#define IOM_GRP_DDRPKE MA(0x020e0758, 0x020e0754, 0x0) +#define IOM_GRP_DDRMODE MA(0x020e0774, 0x020e0760, 0x0) +#define IOM_GRP_CTLDS MA(0x020e078c, 0x020e076c, 0x0) +#define IOM_GRP_DDR_TYPE MA(0x020e0798, 0x020e0774, 0x0) + +#define IRAM_FREE_START 0x00907000 + +#define MMDC_P0_MDCTL 0x021b0000 +#define MMDC_P0_MDPDC 0x021b0004 +#define MMDC_P0_MDOTC 0x021b0008 +#define MMDC_P0_MDCFG0 0x021b000c +#define MMDC_P0_MDCFG1 0x021b0010 +#define MMDC_P0_MDCFG2 0x021b0014 +#define MMDC_P0_MDMISC 0x021b0018 +#define MMDC_P0_MDSCR 0x021b001c +#define MMDC_P0_MDREF 0x021b0020 +#define MMDC_P0_MDRWD 0x021b002c +#define MMDC_P0_MDOR 0x021b0030 +#define MMDC_P0_MDASP 0x021b0040 +#define MMDC_P0_MAPSR 0x021b0404 +#define MMDC_P0_MPZQHWCTRL 0x021b0800 +#define MMDC_P0_MPWLDECTRL0 0x021b080c +#define MMDC_P0_MPWLDECTRL1 0x021b0810 +#define MMDC_P0_MPODTCTRL 0x021b0818 +#define MMDC_P0_MPRDDQBY0DL 0x021b081c +#define MMDC_P0_MPRDDQBY1DL 0x021b0820 +#define MMDC_P0_MPRDDQBY2DL 0x021b0824 +#define MMDC_P0_MPRDDQBY3DL 0x021b0828 +#define MMDC_P0_MPDGCTRL0 0x021b083c +#define MMDC_P0_MPDGCTRL1 0x021b0840 +#define MMDC_P0_MPRDDLCTL 0x021b0848 +#define MMDC_P0_MPWRDLCTL 0x021b0850 +#define MMDC_P0_MPMUR0 0x021b08b8 + +#define MMDC_P1_MDCTL 0x021b4000 +#define MMDC_P1_MDPDC 0x021b4004 +#define MMDC_P1_MDOTC 0x021b4008 +#define MMDC_P1_MDCFG0 0x021b400c +#define MMDC_P1_MDCFG1 0x021b4010 +#define MMDC_P1_MDCFG2 0x021b4014 +#define MMDC_P1_MDMISC 0x021b4018 +#define MMDC_P1_MDSCR 0x021b401c +#define MMDC_P1_MDREF 0x021b4020 +#define MMDC_P1_MDRWD 0x021b402c +#define MMDC_P1_MDOR 0x021b4030 +#define MMDC_P1_MDASP 0x021b4040 +#define MMDC_P1_MAPSR 0x021b4404 +#define MMDC_P1_MPZQHWCTRL 0x021b4800 +#define MMDC_P1_MPWLDECTRL0 0x021b480c +#define MMDC_P1_MPWLDECTRL1 0x021b4810 +#define MMDC_P1_MPODTCTRL 0x021b4818 +#define MMDC_P1_MPRDDQBY0DL 0x021b481c +#define MMDC_P1_MPRDDQBY1DL 0x021b4820 +#define MMDC_P1_MPRDDQBY2DL 0x021b4824 +#define MMDC_P1_MPRDDQBY3DL 0x021b4828 +#define MMDC_P1_MPDGCTRL0 0x021b483c +#define MMDC_P1_MPDGCTRL1 0x021b4840 +#define MMDC_P1_MPRDDLCTL 0x021b4848 +#define MMDC_P1_MPWRDLCTL 0x021b4850 +#define MMDC_P1_MPMUR0 0x021b48b8 + +#define CCM_CCGR0 0x020C4068 +#define CCM_CCGR1 0x020C406c +#define CCM_CCGR2 0x020C4070 +#define CCM_CCGR3 0x020C4074 +#define CCM_CCGR4 0x020C4078 +#define CCM_CCGR5 0x020C407c +#define CCM_CCGR6 0x020C4080 + + +#define WRITE_ENTRY1(addr, q) DATA 4, addr, q +#ifdef CONFIG_MX6Q +#define MA(mx6q, mx6dl_solo, mx6sololite) mx6q +#define WRITE_ENTRY2(addr, q, dl) WRITE_ENTRY1(addr, q) +#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, q) +#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, q) +#else + +#define WRITE_ENTRY2(addr, q, dl) WRITE_ENTRY1(addr, dl) +#ifdef CONFIG_MX6DL +#define MA(mx6q, mx6dl_solo, mx6sololite) mx6dl_solo +#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, dl) +#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, dl) +#else + +#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, solo) +#ifdef CONFIG_MX6S +#define MA(mx6q, mx6dl_solo, mx6sololite) mx6dl_solo +#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, solo) +#else + +#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, sl) +#ifdef CONFIG_MX6SL +#define MA(mx6q, mx6dl_solo, mx6sololite) mx6sololite +#else + +#error "Please select cpu" +#endif /* CONFIG_MX6SL */ +#endif /* CONFIG_MX6S */ +#endif /* CONFIG_MX6DL */ +#endif /* CONFIG_MX6Q */ + +#endif /*__ASM_ARCH_IMX_MKIMAGE_H__ */ diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index c86cd40..84823f8 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -25,6 +25,9 @@ * * The syntax is taken as close as possible with the kwbimage */ +#define __ASSEMBLY__ +#include <config.h> +#include <asm/arch/imx-mkimage.h>
/* image version */ IMAGE_VERSION 2 @@ -46,129 +49,129 @@ BOOT_FROM sd * Address absolute address of the register * value value to be stored in the register */ -DATA 4 0x020e05a8 0x00000030 -DATA 4 0x020e05b0 0x00000030 -DATA 4 0x020e0524 0x00000030 -DATA 4 0x020e051c 0x00000030 - -DATA 4 0x020e0518 0x00000030 -DATA 4 0x020e050c 0x00000030 -DATA 4 0x020e05b8 0x00000030 -DATA 4 0x020e05c0 0x00000030 - -DATA 4 0x020e05ac 0x00020030 -DATA 4 0x020e05b4 0x00020030 -DATA 4 0x020e0528 0x00020030 -DATA 4 0x020e0520 0x00020030 - -DATA 4 0x020e0514 0x00020030 -DATA 4 0x020e0510 0x00020030 -DATA 4 0x020e05bc 0x00020030 -DATA 4 0x020e05c4 0x00020030 - -DATA 4 0x020e056c 0x00020030 -DATA 4 0x020e0578 0x00020030 -DATA 4 0x020e0588 0x00020030 -DATA 4 0x020e0594 0x00020030 - -DATA 4 0x020e057c 0x00020030 -DATA 4 0x020e0590 0x00003000 -DATA 4 0x020e0598 0x00003000 -DATA 4 0x020e058c 0x00000000 - -DATA 4 0x020e059c 0x00003030 -DATA 4 0x020e05a0 0x00003030 -DATA 4 0x020e0784 0x00000030 -DATA 4 0x020e0788 0x00000030 - -DATA 4 0x020e0794 0x00000030 -DATA 4 0x020e079c 0x00000030 -DATA 4 0x020e07a0 0x00000030 -DATA 4 0x020e07a4 0x00000030 - -DATA 4 0x020e07a8 0x00000030 -DATA 4 0x020e0748 0x00000030 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e0750 0x00020000 - -DATA 4 0x020e0758 0x00000000 -DATA 4 0x020e0774 0x00020000 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0798 0x000C0000 - -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 - -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 - -DATA 4 0x021b0018 0x00081740 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538E64 -DATA 4 0x021b0014 0x01FF00DB -DATA 4 0x021b002c 0x000026D2 - -DATA 4 0x021b0030 0x005B0E21 -DATA 4 0x021b0008 0x09444040 -DATA 4 0x021b0004 0x00025576 -DATA 4 0x021b0040 0x00000027 -DATA 4 0x021b0000 0x831A0000 - -DATA 4 0x021b001c 0x04088032 -DATA 4 0x021b001c 0x0408803A -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x0000803B -DATA 4 0x021b001c 0x00428031 -DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x09408030 -DATA 4 0x021b001c 0x09408038 - -DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b001c 0x04008048 -DATA 4 0x021b0800 0xA1380003 -DATA 4 0x021b4800 0xA1380003 -DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00022227 -DATA 4 0x021b4818 0x00022227 - -DATA 4 0x021b083c 0x434B0350 -DATA 4 0x021b0840 0x034C0359 -DATA 4 0x021b483c 0x434B0350 -DATA 4 0x021b4840 0x03650348 -DATA 4 0x021b0848 0x4436383B -DATA 4 0x021b4848 0x39393341 -DATA 4 0x021b0850 0x35373933 -DATA 4 0x021b4850 0x48254A36 - -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F - -DATA 4 0x021b480c 0x00440044 -DATA 4 0x021b4810 0x00440044 - -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 - -DATA 4 0x021b001c 0x00000000 -DATA 4 0x021b0404 0x00011006 +WRITE_ENTRY1(IOM_DRAM_SDQS0, 0x00000030) +WRITE_ENTRY1(IOM_DRAM_SDQS1, 0x00000030) +WRITE_ENTRY1(IOM_DRAM_SDQS2, 0x00000030) +WRITE_ENTRY1(IOM_DRAM_SDQS3, 0x00000030) + +WRITE_ENTRY1(IOM_DRAM_SDQS4, 0x00000030) +WRITE_ENTRY1(IOM_DRAM_SDQS5, 0x00000030) +WRITE_ENTRY1(IOM_DRAM_SDQS6, 0x00000030) +WRITE_ENTRY1(IOM_DRAM_SDQS7, 0x00000030) + +WRITE_ENTRY1(IOM_DRAM_DQM0, 0x00020030) +WRITE_ENTRY1(IOM_DRAM_DQM1, 0x00020030) +WRITE_ENTRY1(IOM_DRAM_DQM2, 0x00020030) +WRITE_ENTRY1(IOM_DRAM_DQM3, 0x00020030) + +WRITE_ENTRY1(IOM_DRAM_DQM4, 0x00020030) +WRITE_ENTRY1(IOM_DRAM_DQM5, 0x00020030) +WRITE_ENTRY1(IOM_DRAM_DQM6, 0x00020030) +WRITE_ENTRY1(IOM_DRAM_DQM7, 0x00020030) + +WRITE_ENTRY1(IOM_DRAM_CAS, 0x00020030) +WRITE_ENTRY1(IOM_DRAM_RAS, 0x00020030) +WRITE_ENTRY1(IOM_DRAM_SDCLK_0, 0x00020030) +WRITE_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030) + +WRITE_ENTRY1(IOM_DRAM_RESET, 0x00020030) +WRITE_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000) +WRITE_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000) +WRITE_ENTRY1(IOM_DRAM_SDBA2, 0x00000000) + +WRITE_ENTRY1(IOM_DRAM_SDODT0, 0x00003030) +WRITE_ENTRY1(IOM_DRAM_SDODT1, 0x00003030) +WRITE_ENTRY1(IOM_GRP_B0DS, 0x00000030) +WRITE_ENTRY1(IOM_GRP_B1DS, 0x00000030) + +WRITE_ENTRY1(IOM_GRP_B2DS, 0x00000030) +WRITE_ENTRY1(IOM_GRP_B3DS, 0x00000030) +WRITE_ENTRY1(IOM_GRP_B4DS, 0x00000030) +WRITE_ENTRY1(IOM_GRP_B5DS, 0x00000030) + +WRITE_ENTRY1(IOM_GRP_B6DS, 0x00000030) +WRITE_ENTRY1(IOM_GRP_B7DS, 0x00000030) +WRITE_ENTRY1(IOM_GRP_ADDDS, 0x00000030) +WRITE_ENTRY1(IOM_DDRMODE_CTL, 0x00020000) + +WRITE_ENTRY1(IOM_GRP_DDRPKE, 0x00000000) +WRITE_ENTRY1(IOM_GRP_DDRMODE, 0x00020000) +WRITE_ENTRY1(IOM_GRP_CTLDS, 0x00000030) +WRITE_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000) + +WRITE_ENTRY1(MMDC_P0_MPRDDQBY0DL, 0x33333333) +WRITE_ENTRY1(MMDC_P0_MPRDDQBY1DL, 0x33333333) +WRITE_ENTRY1(MMDC_P0_MPRDDQBY2DL, 0x33333333) +WRITE_ENTRY1(MMDC_P0_MPRDDQBY3DL, 0x33333333) + +WRITE_ENTRY1(MMDC_P1_MPRDDQBY0DL, 0x33333333) +WRITE_ENTRY1(MMDC_P1_MPRDDQBY1DL, 0x33333333) +WRITE_ENTRY1(MMDC_P1_MPRDDQBY2DL, 0x33333333) +WRITE_ENTRY1(MMDC_P1_MPRDDQBY3DL, 0x33333333) + +WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740) + +WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000) +WRITE_ENTRY1(MMDC_P0_MDCFG0, 0x555A7975) +WRITE_ENTRY1(MMDC_P0_MDCFG1, 0xFF538E64) +WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB) +WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2) + +WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21) +WRITE_ENTRY1(MMDC_P0_MDOTC, 0x09444040) +WRITE_ENTRY1(MMDC_P0_MDPDC, 0x00025576) +WRITE_ENTRY1(MMDC_P0_MDASP, 0x00000027) +WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000) + +WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032) +WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0408803A) +WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033) +WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0000803B) +WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031) +WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428039) +WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030) +WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408038) + +WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040) +WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008048) +WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1380003) +WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1380003) +WRITE_ENTRY1(MMDC_P0_MDREF, 0x00005800) +WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227) +WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227) + +WRITE_ENTRY1(MMDC_P0_MPDGCTRL0, 0x434B0350) +WRITE_ENTRY1(MMDC_P0_MPDGCTRL1, 0x034C0359) +WRITE_ENTRY1(MMDC_P1_MPDGCTRL0, 0x434B0350) +WRITE_ENTRY1(MMDC_P1_MPDGCTRL1, 0x03650348) +WRITE_ENTRY1(MMDC_P0_MPRDDLCTL, 0x4436383B) +WRITE_ENTRY1(MMDC_P1_MPRDDLCTL, 0x39393341) +WRITE_ENTRY1(MMDC_P0_MPWRDLCTL, 0x35373933) +WRITE_ENTRY1(MMDC_P1_MPWRDLCTL, 0x48254A36) + +WRITE_ENTRY1(MMDC_P0_MPWLDECTRL0, 0x001F001F) +WRITE_ENTRY1(MMDC_P0_MPWLDECTRL1, 0x001F001F) + +WRITE_ENTRY1(MMDC_P1_MPWLDECTRL0, 0x00440044) +WRITE_ENTRY1(MMDC_P1_MPWLDECTRL1, 0x00440044) + +WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800) +WRITE_ENTRY1(MMDC_P1_MPMUR0, 0x00000800) + +WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00000000) +WRITE_ENTRY1(MMDC_P0_MAPSR, 0x00011006)
/* set the default clock gate to save power */ -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF +WRITE_ENTRY1(CCM_CCGR0, 0x00C03F3F) +WRITE_ENTRY1(CCM_CCGR1, 0x0030FC03) +WRITE_ENTRY1(CCM_CCGR2, 0x0FFFC000) +WRITE_ENTRY1(CCM_CCGR3, 0x3FF00000) +WRITE_ENTRY1(CCM_CCGR4, 0x00FFF300) +WRITE_ENTRY1(CCM_CCGR5, 0x0F0000C3) +WRITE_ENTRY1(CCM_CCGR6, 0x000003FF)
/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF +WRITE_ENTRY1(IOMUXC_GPR4, 0xF00000CF) /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F +WRITE_ENTRY1(IOMUXC_GPR6, 0x007F007F) +WRITE_ENTRY1(IOMUXC_GPR7, 0x007F007F)