24 Feb
2016
24 Feb
'16
5:47 p.m.
On 02/01/2016 07:36 PM, Mingkai Hu wrote:
From: Mingkai Hu mingkai.hu@nxp.com
Memory controller performance is not optimal with default internal target queue register value, write required value for optimal DDR performance.
Signed-off-by: Mingkai Hu mingkai.hu@nxp.com
v3:
- Move the macro check to soc.c.
v2:
- Add a check to make sure A009660 and A008514 is are not both enabled.
- Add comment for the offset of eddrtqcr1.
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 19 +++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + 2 files changed, 20 insertions(+)
Applied to fsl-qoriq master. Awaiting upstream.
York