On 4/15/20 11:00 AM, Ley Foon Tan wrote:
Change to use reset DM function and remove unused socfpga_reset_deassert_noc_ddr_scheduler().
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
.../include/mach/reset_manager_arria10.h | 1 - arch/arm/mach-socfpga/reset_manager_arria10.c | 7 ------ drivers/ddr/altera/sdram_arria10.c | 25 ++++++++++--------- 3 files changed, 13 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h index 22e4eb33de88..a0fad7c1e2fc 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h @@ -9,7 +9,6 @@ #include <dt-bindings/reset/altr,rst-mgr-a10.h>
void socfpga_watchdog_disable(void); -void socfpga_reset_deassert_noc_ddr_scheduler(void); int socfpga_reset_deassert_bridges_handoff(void); void socfpga_reset_deassert_osc1wd0(void); int socfpga_bridges_reset(void); diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index aa5299415a74..edfe250ec0bc 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -62,13 +62,6 @@ void socfpga_watchdog_disable(void) ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); }
-/* Release NOC ddr scheduler from reset */ -void socfpga_reset_deassert_noc_ddr_scheduler(void) -{
- clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);-}
static int get_bridge_init_val(const void *blob, int compat_id) { int node; diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index a31d45a5bb8e..794c13acfa93 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -10,19 +10,21 @@ #include <fdtdec.h> #include <malloc.h> #include <ram.h> +#include <reset.h> #include <wait_bit.h> #include <watchdog.h> #include <asm/io.h> #include <asm/arch/fpga_manager.h> #include <asm/arch/misc.h> -#include <asm/arch/reset_manager.h> #include <asm/arch/sdram.h> +#include <dm/device_compat.h> #include <linux/kernel.h>
DECLARE_GLOBAL_DATA_PTR;
struct altera_sdram_priv { struct ram_info info;
- struct reset_ctl_bulk resets;
};
struct altera_sdram_platdata { @@ -152,7 +154,7 @@ static int emif_reset(struct altera_sdram_platdata *plat) return 0; }
-static int ddr_setup(struct altera_sdram_platdata *plat) +static int sdram_startup(struct altera_sdram_platdata *plat) { int i, ret;
@@ -198,16 +200,6 @@ static void sdram_init_ecc_bits(u32 size) dcache_disable(); }
-/* Function to startup the SDRAM*/ -static int sdram_startup(struct altera_sdram_platdata *plat) -{
- /* Release NOC ddr scheduler from reset */
- socfpga_reset_deassert_noc_ddr_scheduler();
- /* Bringup the DDR (calibration and configuration) */
- return ddr_setup(plat);
-}
static u64 sdram_size_calc(struct altera_sdram_platdata *plat) { u32 dramaddrw = readl(plat->iohmc + DRAMADDRW); @@ -703,8 +695,17 @@ static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
static int altera_sdram_probe(struct udevice *dev) {
int ret; struct altera_sdram_priv *priv = dev_get_priv(dev);
ret = reset_get_bulk(dev, &priv->resets);
if (ret) {
dev_err(dev, "Can't get reset: %d\n", ret);return -ENODEV;}
reset_deassert_bulk(&priv->resets);
if (ddr_calibration_sequence(dev->platdata) != 0) { puts("SDRAM init failed.\n"); goto failed;
I think you need to re-assert the reset in the failed: fail path.