From: Stephen Warren swarren@nvidia.com
Rev A03 of P2180 requires some PMIC programming adjustments, yet the PMIC's own OTP has not been updated. Consequently, U-Boot must make these changes itself.
NVIDIA's syseng team has confirmed that these changes can be enabled on all board revisions without issue.
Signed-off-by: Stephen Warren swarren@nvidia.com --- board/nvidia/p2371-2180/p2371-2180.c | 22 ++++++++++++++++++++++ board/nvidia/p2571/max77620_init.h | 2 ++ 2 files changed, 24 insertions(+)
diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 0f587eaaa796..dbdc1b65e680 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -30,6 +30,28 @@ void pin_mux_mmc(void) ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); + + /* Disable LDO4 discharge */ + ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) { + printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret); + } else { + val &= ~BIT(1); /* ADE */ + ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret); + } + + /* Set MBLPD */ + ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) { + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } else { + val |= BIT(6); /* MBLPD */ + ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } }
/* diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h index 92c3719112a4..39e550149aae 100644 --- a/board/nvidia/p2571/max77620_init.h +++ b/board/nvidia/p2571/max77620_init.h @@ -13,6 +13,8 @@ #define MAX77620_I2C_ADDR 0x78 #define MAX77620_I2C_ADDR_7BIT 0x3C
+#define MAX77620_CNFGGLBL1_REG 0x00 + #define MAX77620_SD0_REG 0x16 #define MAX77620_SD1_REG 0x17 #define MAX77620_SD2_REG 0x18